Geometrical instruments – Gauge – Collocating
Reexamination Certificate
2003-05-15
2004-08-17
Niebling, John F. (Department: 2812)
Geometrical instruments
Gauge
Collocating
Reexamination Certificate
active
06775920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a semiconductor device including a superposition inspection step for determining properness/improperness of superposed positions of a superposed layer and a resist film employed as a superpositive layer.
2. Description of the Background Art
In a process of fabricating a semiconductor device, a resist film serving as a superpositive layer having a prescribed pattern is provided on a prescribed layer (hereinafter referred to as a superposed layer) for patterning the superposed layer, and employed as a mask for etching the superposed layer or a layer interposed between the superposed layer and the resist film. Therefore, it is important to properly position the resist film with respect to the superposed layer. Thus, it is also important to pattern the resist film itself.
A method of positioning a resist film with respect to a superposed layer
605
is briefly described with reference to
FIGS. 12
to
17
.
FIG. 12
is a plan view schematically showing the structure of a photomask
500
for transferring prescribed patterns to the resist film. The photomask
500
generally comprises wiring pattern regions
501
and
502
provided with wiring patterns for semiconductor devices and a peripheral pattern region
510
, enclosing the wiring pattern regions
501
and
502
, corresponding to a dicing line of a wafer.
The peripheral pattern region
510
is provided with a superposition mark
530
employed for determining properness/improperness of superposed positions of the superposed layer
605
and the resist film.
Specific purposes of superposition marks are now briefly described.
FIG. 13
is a plan view of superposition marks formed on the superposed layer
605
and the resist film respectively, and
FIG. 14
is a sectional view taken along the line XIV—XIV in FIG.
13
. An etched layer
611
is provided with a superposed layer superposition mark
611
H formed to reflect the shapes of holes
605
d
provided on the superposed layer
605
as superposed layer superposition marks, while the resist film is provided with a resist film superposition mark
701
H transferred from the superposition mark
530
of the aforementioned photomask
500
.
A plurality of recesses
611
h
are arranged to form a square thereby defining the overall shape of the superposed layer superposition mark
611
H, and the dimension (H) of one side of the square is about 25 &mgr;m. When formed, the etched layer
611
partially drops into the holes
605
d
provided in the superposed layer
605
, thereby forming the recesses
611
h
. The holes
605
d
are formed through the same step as that of forming contact holes (not shown) in a wiring region of the etched layer
611
.
On the etched layer
611
, the resist film superposition mark
701
H formed on the resist film is provided inside the superposed layer superposition mark
611
H. The dimension (h) of one side of the resist film superposition mark
701
H is about 10 &mgr;m.
A general etching step
800
employing the superposition mark
611
H and
701
H is now described with reference to FIG.
15
. First, a photolithography step is carried out for exposing/etching the resist film (S
810
). Thereafter a superposition inspection step is carried out with the superposed layer superposition mark
611
H and the resist film superposition mark
701
H (S
820
).
In this superposition inspection step (S
820
), a superposition inspection apparatus (not shown) is employed for reading the positions of the superposed layer superposition mark
611
H and the resist film superposition mark
701
h
from image information of these superposition marks
611
H and
701
h
and determining whether or not the resist film superposition mark
701
H is present on a prescribed position (tolerance position) of the superposed layer superposition mark
611
H.
If the resist film superposition mark
701
H is present on the prescribed position of the superposed layer superposition mark
611
H, the superposition marks
611
H and
701
H are determined as acceptable and the process makes a transition to a development inspection step (S
830
). If the superposition marks
611
H and
701
H are rejectable, the resist film is removed so that a new resist film is applied and exposed/etched (S
810
).
Then, a resist dimension inspection step (S
840
) and an applied mask confirmation step (S
850
) are carried out for thereafter executing an etching step for the etched layer
611
through the resist film (S
860
) and making a transition to a subsequent step (S
870
).
However, a method of fabricating a semiconductor device including the aforementioned superposition inspection step has the following problems:
In the process of fabricating a semiconductor device, different photomasks may be employed in the same photolithography step due to revision of the semiconductor device pattern, addition of a type-oriented option or the like.
For example,
FIG. 16
is a sectional view of a semiconductor device including a first semiconductor layer
601
provided with conductive regions
602
,
603
and
604
and an interlayer dielectric film
605
having contact holes
605
a
,
605
b
and
605
c
reaching the conductive regions
602
,
603
and
604
respectively.
Contact plugs
607
,
608
and
609
reaching the conductive regions
602
,
603
and
604
are provided in the contact holes
605
a
,
605
b
and
605
c
respectively. Further, a wiring layer
611
A communicating with the contact plug
607
and a wiring layer
611
B communicating with the contact plugs
608
and
609
are formed on the interlayer dielectric film
605
. The wiring layers
611
A and
611
B are patterned through a resist film
701
A having patterns corresponding to the wiring layers
611
A and
611
B.
FIG. 17
is a sectional view of another semiconductor device having a basic structure identical to that of the aforementioned semiconductor device shown in FIG.
16
. The semiconductor device shown in
FIG. 17
is different from that shown in
FIG. 16
in a point that the same is provided with wiring layers
611
C and
611
D communicating with contact plugs
608
and
609
respectively. Therefore, these wiring layers
611
C and
611
D are patterned through a resist film
701
B having patterns corresponding to a wiring layer
611
A and the wiring layers
611
C and
611
D.
Thus, regions X
1
to X
4
having partially different wiring structures are interspersed as shown in the plan view of
FIG. 12
, for example, and the difference between the wiring structures is confirmed in the applied mask confirmation step (S
850
) carried out in the second half of the etching step
800
shown in FIG.
15
.
This is because all superposition marks are generally shaped identically to each other and provided on identical positions of peripheral pattern regions of photomasks having different patterns and hence it is impossible to determine whether or not the applied photomask
500
is correct in the steps S
820
to S
840
shown in FIG.
15
. Thus, correctness of the applied photomask
500
is confirmed in the second half of the etching step
800
, leading to hindrance of improvement of the working efficiency.
Further, the applied mask confirmation step (S
850
) is generally manually carried out offline, leading to reduction of the fabrication yield for the semiconductor device resulting from overlook of incorrectness of the photomask
500
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.
In order to attain the aforementioned object, the inventive method of fabricating a semiconductor device including a superposition inspection step for determining properness/improperness of a superposed position of a resist film formed on a superposed layer as a superposit
Kido Shigenori
Kishida Takeshi
McDermott Will & Emery LLP
Niebling John F.
Renesas Technology Corp.
Stevenson Andre′ C.
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