Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1996-05-02
1998-12-29
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257514, 257515, 257520, 257521, 438151, 438197, 438226, 438701, 438713, H01L 2792
Patent
active
058545093
ABSTRACT:
Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (1), thereby forming a groove (20). Thereafter silicon is epitaxially grown in the groove (20), thereby forming an epitaxial silicon layer (4). An NMOS transistor is formed on an upper layer part of the epitaxial silicon layer (4). At this time, the taper of the groove (20) is located under a part of an n.sup.+ layer (8) forming the NMOS transistor. Thus, a method of fabricating a semiconductor device capable of performing element isolation with neither halation nor formation of bird's beak in fabrication while minimizing a leakage current flowing across elements is obtained.
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Joachim N. Burghartz, et al, "Partial-SOI Isolation Structure for Reduced Bipolar Transistor Parasitics", IEEE Electron Device Letters, vol. 13, No. 8, Aug. 1992.
IEDM, pp. 479-482, 1993, P.U. Kenkare, et al., "Sensitivity of Field Isolation Profiles ot Active Pattern" Jan.
J. Electrochem. Soc., vol. 136, No. 12, pp. 3815-3820, Dec. 1989, R. L. Guldi, et al., "Characterization of Poly-Buffered Locos in Manufacturing Environment".
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward
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