Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2000-10-20

2002-01-22

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S238000, C438S435000, C257S263000

Reexamination Certificate

active

06340623

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device which involves simplified processing steps while ensuring improved device reliability.
(b) Description of the Related Art
Generally, semiconductor devices are fabricated through isolating active regions from field regions at a semiconductor substrate, and forming numerous devices such as transistors at the isolated active regions on the substrate.
In order to perform the device isolation, a local oxidation of silicon (LOCOS) technique has been widely used in the semiconductor fabrication process. In the LOCOS technique, the semiconductor substrate itself suffers thermal oxidation using a nitride layer as a mask. However, in the application of the LOCOS technique, the so-called bird's beak occurs, and the device isolation area takes a large volume that limits device miniaturization.
In this connection, a shallow trench isolation (STI) technique has been suggested to replace the LOCOS technique. In the STI technique, shallow trenchs are made at the semiconductor substrate, and filled with an insulating material. In this way, the field regions can be limited to the relatively narrow trench formation area while making it possible to miniaturize the device dimension as much as possible.
FIGS. 1A
to
1
E sequentially illustrate the steps of fabricating a semiconductor device according to a prior art method.
As shown in
FIG. 1A
, a pad oxide layer
2
, and a silicon nitride layer
3
are sequentially deposited onto a semiconductor substrate
1
, and a moat pattern
4
is formed on the silicon nitride layer
3
. The silicon nitride
3
, the pad oxide layer
2
, and the semiconductor substrate
1
are etched through photolithography using the moat pattern
4
as a mask to thereby form trenches
5
. At this time, the semiconductor substrate
1
is partially etched to a desired depth. Thereafter, the moat pattern
4
is removed, and as shown in
FIG. 1B
, a trench thermal-oxide layer
6
is formed on the inner wall (specifically, a floor and sidewalls) of each trench
5
. The trenches
5
are then filled up through forming a trench oxide layer
7
onto the entire surface of the semiconductor substrate
1
using an atmospheric pressure chemical vapor deposition (APCVD) technique. Then, a reverse moat pattern
8
the phase of which is reversed by 180 degree compared to the moat pattern
4
is formed on the trench oxide layer
7
.
The trench oxide layer
7
is then etched through photolithography using the reverse moat pattern
8
as a mask to thereby expose the underlying silicon nitride layer
3
to the outside. The reverse moat pattern
8
is removed, and as shown in
FIG. 1C
, the trench oxide layer
7
is planarized through chemical mechanical polishing (CMP) using the silicon nitride layer
3
as a buffer.
As shown in
FIG. 1D
, the silicon nitride layer
3
is removed through wet etching to thereby complete the trench isolation process. Thereafter, ion implantation for controlling threshold voltage, ion implantation for preventing punch-through, ion implantation for channel formation, and ion implantation for well formation are performed with respect to the semiconductor substrate
1
.
As shown in
FIG. 1E
, the pad oxide layer
2
that is damaged due to the ion implantation is removed, and metal oxide semiconductor (MOS) devices
9
are formed at the active regions of the semiconductor substrate
1
. Each MOS device is formed with a source
9
a
, a drain
9
b
, and a gate electrode
9
c.
As shown in
FIG. 1F
, an insulating layer
10
is formed on the entire surface of the semiconductor substrate
1
with the MOS devices
9
, and planarized through CMP.
In the above process, when the trench oxide layer
7
is planarized through CMP, torn oxide or scratches may occur, resulting in deteriorated device reliability.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a semiconductor device which involves simplified processing steps while preventing processing failure accruing to chemical mechanical polishing.
These and other objects may be achieved by a method in accordance with the present invention of fabricating a semiconductor device. In one embodiment, a plurality of devices are first formed at the semiconductor substrate, and an insulating layer is then deposited onto the substrate with the devices. Trenches are formed at the substrate for electrically isolating one device from another.


REFERENCES:
patent: 5225358 (1993-07-01), Pasch
patent: 5453635 (1995-09-01), Hsu et al.
patent: 5472894 (1995-12-01), Hsu et al.
patent: 5789769 (1998-08-01), Yamazaki
patent: 5879980 (1999-03-01), Selcuk et al.
patent: 5972758 (1999-10-01), Liang
patent: 6020621 (2000-02-01), Wu
patent: 6184105 (2001-02-01), Liu et al.

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