Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-02-29
2001-06-26
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S613000, C438S737000, C438S754000
Reexamination Certificate
active
06251797
ABSTRACT:
This application is based on an application No. 11-51207 filed in Japan, the content of which is incorporated hereinto by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device in which a method of forming a bump provided as connecting means on the surface of the semiconductor device is improved.
2. Description of the Related Art
In fabricating a semiconductor device, a bump forming step is carried out after a wiring forming step for forming predetermined wiring and a protective film forming step for forming a protective film on the surface of a semiconductor substrate are terminated.
In the bump forming step, a series of processing such as sputtering, photolithography, plating, resist stripping, etching, and annealing is performed.
Specifically, description is made with reference to
FIGS. 1A
to
1
E.
A TiW barrier layer
3
and an Au seed layer
4
are continuously formed, respectively, by sputtering on an aluminum electrode
2
exposed from a hole la formed in a protective film
1
. The barrier layer
3
and the seed layer
4
are formed so as to cover not only the surface of the electrode
2
but also the surface of the protective film
1
(FIG.
1
A).
A resist
5
is then formed such that only an upper part of the electrode
2
is exposed by photolithography (FIG.
1
B).
After the resist
5
is formed, a bump
6
is provided by plating (FIG.
1
C).
After the bump
6
is formed, the resist
5
is stripped (FIG.
1
D).
Thereafter, unnecessary parts of the seed layer
4
and the barrier layer
3
are etched away. The surface of the bump
6
is slightly ground as the etching is performed (FIG.
1
E). The semiconductor substrate is finally baked by an oven.
In the conventional steps of fabricating the semiconductor device, the bump forming step comprising the series of processing is carried out after the protective film forming step is terminated, as described above. Accordingly, the number of steps of fabricating the semiconductor device is large, so that a time period required for the fabrication is lengthened.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve such problems and has for its one object to shorten a time period required to fabricate a semiconductor.
Another object of the present invention is to provide a method of fabricating a semiconductor, in which a bump can be formed, more simply than that in a conventional example, by improving a bump forming step.
The present invention is directed to a method of fabricating a semiconductor device, characterized in that the step of forming wiring on the surface of a semiconductor substrate comprises the steps of forming a conductive film for wiring, stacking on the formed conductive film a barrier layer and a seed layer which are required to form a bump later in this order, and patterning the conductive film for wiring on which the barrier layer and the seed layer have been stacked, to form wiring, covering the surface of the semiconductor substrate on which the wiring has been formed with a protective film, and forming an opening in the protective film on the wiring, to expose as an electrode the surface of the wiring on which the barrier layer and the seed layer have been stacked.
In the above-mentioned method, it is preferable that the bump is directly formed in a self-alignment manner by electroless plating on the seed layer exposed as the electrode.
According to the present invention, in the wiring forming step, a conductive film for wiring, an aluminum film, for example, is coated by sputtering, for example. A TiW barrier layer, for example, is further stacked thereon, and an Au seed layer, for example, is further stacked thereon.
A stacked film comprising the conductive film, the barrier layer and the seed layer is formed into a wiring pattern by photolithography, for example.
As a result, the barrier layer and the seed layer which are used for forming a bump later are previously formed in a portion, which is exposed as an electrode from the surface of the semiconductor substrate, of the formed wiring pattern.
In thus forming the wiring pattern, if the barrier layer and the seed layer for forming the bump are previously stacked, a desired barrier layer and a desired seed layer are simultaneously obtained by photolithography for patterning the wiring, for example.
The barrier layer and the seed layer are previously stacked on the surface of the electrode. Accordingly, the seed layer is subjected to electroless plating, thereby making it possible to directly grow the bump in a self-alignment manner on the seed layer on the surface of the electrode using the protective film as a resist.
The same processing as normal wiring formation may be only performed except that the seed layer for forming the bump is formed by film forming processing such that at the time of forming the conductive film in forming the wiring, the seed layer is stacked on the surface of the conductive film, as described above. If the seed layer forming processing is previously performed, the seed layer for forming the bump is provided on the surface of the electrode at the time point where the wiring formation and protective film formation processing are terminated.
Accordingly, the bump can be easily formed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5236870 (1993-08-01), Sakata et al.
patent: 5462638 (1995-10-01), Datta et al.
patent: 5508229 (1996-04-01), Baker
patent: 5773359 (1998-06-01), Mitchell et al.
patent: 6028011 (2000-02-01), Takase et al.
Powell William
Rader Fishman & Grauer
Rohm & Co., Ltd.
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