Semiconductor device manufacturing: process – Forming schottky junction
Reexamination Certificate
2007-12-13
2011-10-04
Gurley, Lynne (Department: 2811)
Semiconductor device manufacturing: process
Forming schottky junction
C438S571000, C257S073000, C257S281000, C257S284000, C257SE21368
Reexamination Certificate
active
08030193
ABSTRACT:
To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening. Since the second impurity element is added through the second opening, the periphery of the second opening is also doped with a slight amount of the second impurity element. Therefore, the first impurity region and the second wiring are located away a short distance from each other such that they are not shorted.
REFERENCES:
patent: 4566021 (1986-01-01), Yokoyama
patent: 6825105 (2004-11-01), Grover et al.
patent: 2005/0133605 (2005-06-01), Koyama et al.
patent: 56-049576 (1981-05-01), None
patent: 57-113289 (1982-07-01), None
patent: 02-178973 (1990-07-01), None
patent: 2002-231969 (2002-08-01), None
Isobe Atsuo
Ozawa Suguru
Costellia Jeffrey L.
Gebremariam Samuel
Gurley Lynne
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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