Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-03-29
2005-03-29
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S429000, C438S692000, C438S437000
Reexamination Certificate
active
06872632
ABSTRACT:
A method of fabricating a semiconductor device capable of suppressing defective etching in formation of a deep trench also when the number of polishing steps is reduced is obtained. This method of fabricating a semiconductor device comprises steps of forming a first trench on an element isolation region of a semiconductor substrate, forming a first film consisting of an insulator film to fill up the first trench, forming a second trench larger in depth than the first trench in the first trench, forming an embedded film in the second trench and substantially simultaneously polishing an excess depositional portion of the first film and an excess depositional portion of the embedded film.
REFERENCES:
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patent: 6461934 (2002-10-01), Nishida et al.
patent: 20010036705 (2001-11-01), Nishida et al.
patent: 4-81029 (1992-03-01), None
patent: 5-109880 (1993-04-01), None
patent: 9-8119 (1997-01-01), None
patent: P2000-49296 (2000-02-01), None
Everhart Caridad
McDermott Will & Emery LLP
Sanyo Electric Co,. Ltd.
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