Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2002-08-19

2004-08-24

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S720000

Reexamination Certificate

active

06780779

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device having multilayer interconnects.
Recently remarkably developed semiconductor process techniques have enabled super refinement and high integration of interconnects and semiconductor devices, and hence, ULSIs have been largely improved in their performance.
In accordance with improvement in the integration of interconnects, however, the operation speed of a device has become restricted by delay of a signal on an interconnect.
Accordingly, in a ULSI of the 0.25 &mgr;m generation or later, SiO
2
(with a dielectric constant &egr; of 4.3) conventionally used as a material for an interlayer insulating film is to be replaced with another material with a smaller dielectric constant, such as SiOF doped with fluorine (&egr;=3.5) and SiO:C including an organic substance (&egr;=2.8 through 3.2) (hereinafter referred to as organic SOG).
Now, a method of fabricating a semiconductor device in which the dielectric constant between interconnects is reduced by using organic SOG disclosed in Japanese Laid-Open Patent Publication No. 9-82799 will be described with reference to FIGS.
34
(
a
) through
34
(
e
).
First, as is shown in FIG.
34
(
a
), an aluminum alloy film with a thickness of 500 nm is deposited on a semiconductor substrate
10
, and a first SiOF film (including 6 atom % of fluorine and having a dielectric constant of 3) with a thickness of 200 nm is then deposited on the aluminum alloy film by plasma enhanced CVD. Next, the first SiOF film is patterned into a mask pattern
12
by using a resist pattern as a mask, the resist pattern is then removed, and the aluminum alloy film is patterned into lower-layer interconnects
11
(with a minimum line spacing of 300 nm) by using the mask pattern
12
.
Then, as is shown in FIG.
34
(
b
), a second SiOF film
13
(including 6 atom % of fluorine and having a dielectric constant of 3) with a thickness of 100 nm is deposited on the entire surface of the semiconductor substrate
10
by the plasma enhanced CVD. An organic SOG film
14
(having a dielectric constant of 3) with a thickness of 750 nm is then deposited on the second SiOF film
13
, and the organic SOG film
14
is locally flattened.
Next, as is shown in FIG.
34
(
c
), the organic SOG film
14
is entirely flattened by CMP using an abrasive of pH 9 including dispersed noncrystal cerium oxide, thereby forming a first interlayer insulating film
14
A. In this case, the CMP is carried out until a portion of the organic SOG film
14
above the lower-layer interconnects
11
is removed, but the lower-layer interconnects
11
are never exposed because the second SiOF film
13
works as an etching stopper.
Then, as is shown in FIG.
34
(
d
), a second interlayer insulating film
15
of a silicon oxide film is deposited on the entire surface of the semiconductor substrate
10
by the plasma enhanced CVD.
Thereafter, as is shown in FIG.
34
(
e
), via holes
15
a
are formed in the second interlayer insulating film
15
, and upper-layer interconnects
16
connected to the lower-layer interconnects
11
through the via holes
15
a
are formed on the second interlayer insulating film
15
.
In a semiconductor device fabricated as described above, parasitic capacity between the lower-layer interconnects
11
having the minimum line spacing therebetween is measured, resulting in finding that the dielectric constant is 3 and that the parasitic capacity is small.
The conventional method of fabricating a semiconductor device has, however, the following problems when the line width of the lower-layer interconnect
11
is designed to be the same as the dimension of the via hole
15
a
and alignment shift is caused in the photolithography for forming the via holes
15
a:
FIG. 35
shows the structure of a via hole
17
formed when the alignment shift is caused. When the alignment is shifted, a portion to be etched is shifted from the upper face of the lower-layer interconnect
11
and the etching proceeds to the second SiOF film
13
and the first interlayer insulating film
14
A. Therefore, not only the contact area between the via hole
17
and the lower-layer interconnect
11
is reduced but also the aspect ratio of the via hole
17
is increased. When the aspect ratio of the via hole
17
is increased, a cavity is formed in the upper-layer interconnect
16
during the formation thereof (see FIG.
34
(
e
)), and a gas is generated from the organic SOG film used for forming the first interlayer insulating film
14
A. As a result, a via contact defect can be disadvantageously caused.
SUMMARY OF THE INVENTION
In consideration of the aforementioned conventional problems, an object of the invention is, in a method of fabricating a semiconductor device designed to have a width of a metal interconnect the same as a dimension of a via hole connected to the upper face of the metal interconnect, preventing position shift of a via contact against the metal interconnect even when alignment shift is caused in a mask pattern used for forming the via hole.
In order to achieve the object, the first method of fabricating a semiconductor device of this invention comprises the steps of successively depositing a first metal film and a first interlayer insulating film on an insulating film formed on a semiconductor substrate; forming a first mask pattern for masking first metal interconnect forming areas on the first interlayer insulating film, and etching the first interlayer insulating film and the first metal film by using the first mask pattern, whereby forming openings in the first interlayer insulating film and forming first metal interconnects from the first metal film; filling a second interlayer insulating film made from a different material from the first interlayer insulating film in the openings of the first interlayer insulating film; forming a second mask pattern having via openings corresponding to via hole forming areas on the first interlayer insulating film and the second interlayer insulating film; etching the first interlayer insulating film by using the second mask pattern under etching conditions that an etching rate for the first interlayer insulating film is higher than an etching rate for the second interlayer insulating film, whereby forming via holes for exposing the first metal interconnects in the second interlayer insulating film; depositing a second metal film on the first interlayer insulating film and the second interlayer insulating film so as to fill the via holes; depositing a third interlayer insulating film on the second metal film; forming a third mask pattern for masking second metal interconnect forming areas on the third interlayer insulating film, and etching the second interlayer insulating film and the second metal film by using the third mask pattern, whereby forming openings in the third interlayer insulating film and forming second metal interconnects from the second metal film; and filling a fourth interlayer insulating film in an interval in the second metal interconnects and in the openings of the third interlayer insulating film.
In the first method of fabricating a semiconductor device, the first interlayer insulating film and the first metal film are etched by using the first mask pattern, so as to form the openings in the first interlayer insulating film and form the first metal interconnects from the first metal film. Therefore, the width of the opening of the first interlayer insulating film accords with the line width of the first metal interconnect. Accordingly, the space in the second interlayer insulating film filled in the openings of the first interlayer insulating film accords with the line width of the first metal interconnect.
Therefore, when the via holes are formed in the second interlayer insulating film by etching the first interlayer insulating film by using the second mask pattern having the via openings under etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for

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