Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
2000-11-30
2004-09-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
C438S129000, C438S130000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06794201
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device, and in particular to a semiconductor device employing a field effect transistor that operates at an ultra-high frequency band in the GHz (Giga Hertz) range.
Conventionally, a semiconductor device employing a field effect transistor (hereinafter, referred to as FET) that operates at an ultra-high frequency in the GHz range generally has a structure as shown in
FIG. 13
, for example.
FIG. 13
is a pattern perspective view showing a conventional semiconductor device (an FET chip) when viewed from the top. At this semiconductor device, a plurality of unit FETs
200
are disposed in a line.
A unit FET
200
is provided on an active layer
202
formed on an underlying substrate. This unit FET
200
comprises a basic structure
100
having a source electrode
204
, a drain electrode
206
and a gate electrode
208
(FIGS.
14
A-
14
E). The gate electrode
208
is composed of an electrode section
208
a
and a gate finger
208
b
. The gate finger
208
b
is disposed between the source electrode
204
and the drain electrode
206
. In addition, adjacent unit FETs
200
each share the source electrode
204
and the drain electrode
206
. The gate finger
208
b
is continuous with the electrode section
208
a
, and the electrode section
208
a
is connected to a gate pad
212
that is a power supply point via a first contact hole
210
that penetrates an inter-layer insulating film formed on the gate electrode
208
. The source electrode
204
is connected to a source pad
216
via a second contact hole
214
that penetrates an inter-layer insulating film formed thereon. The drain electrode
206
is connected to a first drain pad
220
via a third contact hole
218
that penetrates an inter-layer insulating film formed thereon. Further, this first drain pad
220
is connected to a second drain pad
224
on an air bridge wiring
222
formed so as to extend to the gate pad
212
.
Now, a method of fabricating this semiconductor device will be described with reference to
FIGS. 14A-14E
.
FIGS. 14A-14E
are schematic views showing the structure in each of the main steps which are carried out to form a basic structure
100
of a unit FET.
First, a wafer that is a substrate
300
is provided. Then, an active layer
202
is formed by using an epitaxial growth or an ion implantation method on this substrate
300
. Here, an n-type channel layer
302
and an n
+
contact layer
304
are formed as the active layer
202
. Next, a source electrode
204
and a drain electrode
206
that are two ohmic electrodes consisting of a metal made of three layers, i.e., AuGe, Ni, and Au layers are formed in an active region of the active layer
202
(FIG.
14
A). Thereafter, an SiO
2
mask having an opening is provided on the active layer region that includes these electrodes, and then, a region of the n
−
contact layer
304
is etched by employing this mask. In this manner, a wide recess
306
that exposes a region of a part of the n-type channel
302
is formed such that a portion
304
x
of an n
+
contact layer
304
remains (FIG.
14
B). Thereafter, an SiO
2
film is further formed at the upper side of the active layer that includes the inside of the wide recess
306
, and an opening
308
a
having a smaller opening diameter than the above wide recess
306
is provided, thereby forming a mask
308
. Etching is carried out by employing this mask
308
, and a narrow recess
310
having a part of the n-type channel layer
302
removed therefrom is formed in the wide recess
306
(FIG.
14
C). Next, a gate metal
312
is spatter-deposited on the entire surface, and is embedded in the narrow recess
310
(FIG.
14
D). Subsequently, the gate metal
312
is processed so as to have the configuration of the gate metal
208
by employing dry etching, and then, the mask
308
of the SiO
2
film is removed (FIG.
14
E). In this manner, the basic structure
100
of the unit FET is obtained.
This basic structure is employed as a TEG-FET (Test Element Group-Field effect transistor), its characteristics are measured, and the characteristics of the finally obtained FET is predicted. Thereafter, an inter-layer insulating film is formed so as to cover the ohmic electrodes
204
and
206
and the gate electrode
208
. Thereafter, first to third contact holes
210
,
214
, and
218
are formed at the inter-layer insulating film so as to expose the two ohmic electrodes
204
and
206
and the gate electrode
208
. Next, a first wiring is formed so as to fill a contact hole. In this step of forming the first wiring, the source pad
216
, first drain pad
220
, second drain pad
224
, and gate pad
212
shown in
FIG. 13
, are formed.
A part of the source pad
216
fills the second contact hole
214
that exposes a surface of the source electrode
204
, and is connected to the source electrode
204
. Similarly, a part of the first drain pad
220
fills the third contact hole
218
that exposes a surface of the drain electrode
206
, and is connected to the drain electrode
206
. In addition, a part of the gate pad
212
fills the first contact hole
210
that exposes the gate electrode
208
, and is connected to the gate electrode
208
. When a structure having this first wiring formed therein is viewed from the top in a planar manner, the first drain pad
220
and the second drain pad
224
are disposed at both sides while the gate pad
212
is sandwiched between these pads (FIG.
13
).
After the first wiring has been formed, an air bridge wiring
222
that connects the first drain pad
220
and the second drain pad
224
to each other is formed as a second wiring. This air bridge wiring
222
is formed so as to encompass the gate pad
212
, and the first and second drain pads
220
and
224
are connected to each other (FIG.
13
).
Thereafter, a passivation film (not shown) is formed on the top surface of the structure.
A semiconductor device using the FET is formed by using the steps as has been described above.
In the semiconductor device with the above-described structure, the size of the FET, in particular, the gate width is determined by a width of the active region and the number of gate fingers. Therefore, the gate width depends on patterns of two masks; a mask employed for forming an active layer initially provided; and a mask for forming a gate electrode and a gate finger. When excess etching is carried out at the step of carrying out recess etching during the FET fabricating, for example, in an active region, the thickness of the active layer is reduced. Thus, there is a risk that a desired drain current value cannot be ensured. In contrast, in the case of insufficient etching, the thickness of the active layer is increased, and a drain current of equal to or more than the set value flows out.
Even if it is judged that an excess or shortage occurs with the drain current value by virtue of the aforementioned reason, as a result of measuring the characteristics of this TEG-FET, at a time when the basic structure
100
of the FET (TEG-FET) is formed, although a threshold voltage of the TEG-FET is a value within a desired range, this excess or shortage cannot be compensated for during the subsequent steps. Therefore, there is a risk that the FET cannot achieve its desired output characteristics. In addition, the FET having low output characteristics is faulty, and thus, there is a risk that the yield of a wafer lot is decreased.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a semiconductor device that enables improvement of degraded characteristics after the characteristics of the TEG-FET has been measured.
In the present invention, when a semiconductor device having a structure in which a plurality of unit FETs are arranged in a line is fabricated, the number of the unit FETs in which a desired drain current value is obtained is first designed in advance. For example, this number is defined as ‘p’. Next, a number ‘m’ of basic structures of unit FETs are formed,
Fourson George
Oki Electric Industry Co. Ltd.
Pham Thanh V
Rabin & Berdo P.C.
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