Semiconductor device manufacturing: process – Forming schottky junction
Reexamination Certificate
1999-07-29
2001-07-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming schottky junction
C438S092000, C438S167000
Reexamination Certificate
active
06261932
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating semiconductor devices. In particular, the present invention relates to the steps associated with the fabrication of bipolar, Metal Oxide Semiconductor (MOS), and Bipolar Complementary MOS (BiCMOS) structures. More particularly, the present invention relates to those aspects of the fabrication of BiCMOS structures involving the formation of Schottky diodes of selectable characteristics without modification of the existing fabrication steps. The present invention is a “no cost” method of fabricating improved Schottky diode structures.
2. Description of the Prior Art
In an effort to create increasingly faster semiconductor devices that consume less power, it is a goal in the semiconductor industry to create increasingly smaller integrated circuit (IC) devices. This relates to the interest in creating IC devices requiring lower supply voltages; that is as device power supplies move from a nominal 5.0 volts to a nominal 3.3 volts, to a nominal 2.0 volts and less. To that end, the steps associated with the fabrication of IC devices are becoming more critical and complex. With increasing complexity and criticality comes significant potential for a decrease in productivity, including greater fabrication costs and lower device yield. It is therefore a continuing goal in this field to minimize fabrication steps and the time and errors associated therewith.
Improvements are sought in all areas of semiconductor fabrication, particularly so in advanced processes. In the field of advanced BiCMOS devices for example, the integration of the steps associated with the formation of bipolar devices and MOS devices creates the type of complexity that requires considerable fabrication coordination. The addition of more masks, implants, depositions, etchings, and the like for advanced BiCMOS processing increases the costs associated with raw materials, capital equipment, and direct and indirect labor obligations.
As power source potentials decrease, there will be a rise in the need for P-N junction devices such as P-N diodes having lower forward turn-on potentials (Vf) with relatively low reverse bias leakage currents (Ir). In that regard, most existing P-N junction devices have Vf and Ir values that would otherwise be unacceptable in systems powered by voltage sources having a nominal potential of 3.3 volts or less, for example. Specifically, most such junction structures have a Vf of about 0.75 volts for a forward current (If) of about 1.0 &mgr;A/&mgr;m
2
. That turn-on potential offers little leeway as the swing between high and low logic levels decreases with lower potentials of the high-potential power rail. It is also to be noted that reverse leakage current leads to power consumption out of line with the importance of most P-N junction diodes as power availability is reduced.
Schottky diodes, formed at the junction of metal-silicon interfaces, can provide a solution to the turn-on voltage limitations of standard P-N diodes. In BiCMOS fabrication processes they are formed at the surface of an active region of the semiconductor wafer by depositing a metal such as Titanium or Platinum onto an area doped with a dopant at a selected concentration. The metal and the silicon react at the surface of the active region under thermal annealing conditions so as to form a metal-silicide layer. For the most part, Schottky diodes are made with an underlying layer of N-type dopant forming the cathode. Of course, a P-type dopant may also be employed to establish the cathode region of the Schottky diode. In either case, it is generally preferable to provide the cathode region with dopant at a concentration somewhat less than that of source and drain regions of a CMOS structure, for example, in order to provide suitable resistance and capacitance characteristics.
It has been determined that of the two metals noted above, the application of Titanium to create a Titanium-silicide (TiSi2) anode may be used to produce a Schottky diode having a Vf equal to about 0.28 volts at If=1.0 &mgr;A/&mgr;m
2
. However, its Ir is about 80 &mgr;A/&mgr;m
2
—a value considered to be too high for the lower-potential supply rails coming on line. Alternatively, a Platinum-silicide (PtSi) anode has an Ir of only about 0.004 &mgr;A/&mgr;m
2
, while its Vf is unacceptably high at about 0.60 volts at If=1.0 &mgr;A/&mgr;m
2
. Therefore, it would be desirable either to adjust the TiSi2-based Schottky to have a lower Ir with substantially the same Vf, or to adjust the PtSi-based Schottky to have a lower Vf with substantially the same Ir.
Several techniques have been described as means to improve some characteristics of Schottky diodes including silicided anodes. These techniques are described, to an extent, in U.S. Pat. No. 4,310,362 issued to Roche et al. and U.S. Pat. No. 5,150,177 issued to Robinson et al. Roche apparently shows that a surface implant may be used to modulate electrical performance. Robinson teaches modulation of the Vf of a Schottky diode using the epitaxial layer as a substrate and with additional doping thereof. However, neither teaches the need to provide the capability to resolve both the Vf and the Ir deficiencies of increasing importance with the continuing trend toward lower-potential supply rails. As importantly, they are riot “no cost” solutions for fabricating suitable Schottky diode structures. Robinson in particular requires additional process steps and modifications to generate a Schottky with lower turn-on values. Therefore, in general, while other solutions may be contemplated to resolve these deficiencies, it is important and preferable that they be resolved substantially within the context of existing fabrication steps so as to avoid adding cost to the process of making a suitable structure.
It is well known that in order to establish desired conductive and non-conductive regions that re designed to either be coupled to, or isolated from, one another, many fabrication steps are required. Although there are any number of fabrication processes suitable for the formation of completed semiconductor devices including Schottky diodes, a summary of 20 major processing events in an exemplar BiCMOS process are set out below, with a brief description of the steps to follow. Those steps, identified by the mask designations noted, are substantially as follows:
Mask No.
Mask Function
1.0
N+ Buried Layer Mask
2.0
P+ Buried Layer Mask
3.0
Composite Mask
4.0
Sink Implant Mask
5.0
Channel Stop and PWell Mask
6.0
P-type Anti-punch Through & Threshold Adjust Mask
7.0
N-type Anti-punch Through & Threshold Adjust Mask
8.0
Base Definition Mask
9.0
N+ Polysilicon Exclusion Mask
10.0
Polycrystalline Silicon Gate Definition Mask
11.0
N LDD Mask
12.0
P LDD Mask
13.0
P+ Source/Drain Definition Mask (PMOS)
14.0
N+ Source/Drain Definition Mask (NMOS)
15.0
Salicide Oxide Mask
16.0
Contact Definition Mask
17.0
METAL 1 (M1) Definition Mask
18.0
VIA Definition Mask
19.0
METAL 2 (M2) Definition Mask
20.0
Bond Pad Definition Mask
Of course, each one of the noted steps includes a plurality of sub-steps, some more so than others. While there are many steps and stages associated with the complete fabrication of an integrated circuit on a semiconductor wafer, a number of the mask stages set out above and described briefly herein are directly applicable to the present invention.
Initially, alignment keys are established in the wafer to align all subsequent steps. Next, for a BiCMOS device including an NPN bipolar transistor, for example, a buried collector layer is created on the substrate of semiconductor material noted above. For that particular type of bipolar transistor, a substrate of P type semiconductor material is used. This is accomplished by introducing, such as by implantation, an N concentration of relatively slow diffusing N type atoms to form an underlying layer for subsequent retrograde diffusion in the substrate. At the same t
Atwood Pierce
Caseiro Chris A.
Fairchild Semiconductor Corp.
Lattin Christopher
Niebling John F.
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