Method of fabricating rugged capacitor of high density DRAMs

Details Method of fabricating rugged capacitor of high density DRAMs Method of fabricating rugged capacitor of high density DRAMs

1998-05-20

1999-07-13

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, H01L 218242

Patent

active

059239891

ABSTRACT:
A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielectric layer and a third polysilicon layer as top electrodes of the capacitors are sequentially formed to complete the rugged capacitor for high density DRAM applications.

REFERENCES:
patent: 5358888 (1994-10-01), Ahn et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 5622889 (1997-04-01), Yoo et al.
patent: 5726085 (1998-03-01), Crenshaw et al.

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