Method of fabricating reliable laminate flip-chip assembly

Details Method of fabricating reliable laminate flip-chip assembly Method of fabricating reliable laminate flip-chip assembly

2002-02-05

2003-10-14

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S015000

Reexamination Certificate

active

06632690

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of forming a package assembly, and more particularly, to a method of underfilling that improves the solder joint reliability in a semiconductor package assembly.
BACKGROUND OF THE INVENTION
A commonly used method to attach silicon chips to laminate substrates, or packages, is known as flip-chip bonding. One such process is the controlled columnar collapsed connection (C4) technique. Typically, a semiconductor die or flip-chip is provided with a pattern of solder bumps or balls on an underside or circuit side thereof. The solder balls are registered with plated or screen printed solder pads on the laminate substrate. Flux is normally supplied between the solder balls and solder pads. Upon heating, the solder pads on the substrate reflow and physically connect with the solder balls on the underside of the chip.
Since a flip-chip is not necessarily encapsulated in a plastic or ceramic package, the connections between the substrate and the chip can fatigue. Fatiguing is the cause of solder joint failure. To prevent this fatigue, a special liquid epoxy is allowed to flow and completely cover the underside of the chip. This is referred to as the “underfill” operation. Upon curing, the resulting encapsulation serves to prevent fatiguing of the electrical interconnects between the laminate substrate and the chip. The epoxy also serves to protect the bonds between a deformed solder pad and solder balls by providing thermal stress relief, i.e. accommodating differential rates of thermal expansion and contraction. This is needed because the laminate substrate can be an organic package that has a much different co-efficient of thermal expansion than the silicon chip. During actual operation of the device, the thermal stresses created cause both the silicon chip and the organic package to be heated. Due to the high thermal mismatch, the thermal stresses make the thermal stress relief provided by underfill a necessity.
In order to ensure continued solder joint reliability, enough of the underfill material needs to be dispensed to form fillets on the sides of the semiconductor die. Ideally, such fillets cover the entire sides, of each of the four sides of the semiconductor die. However, such 100% coverage of the sides of the semiconductor die by the fillets has been difficult to achieve in practice. Some attempts have been made to employ molds, but these methods have proven to be unsuccessful. Another method has been to provide multiple dispensing steps to underfill underneath the semiconductor die and to complete the filling and formation of the fillets in a separate dispensing step. This process has proven unwieldy, and involves expensive extra processing steps that increase the costs of manufacture.
A single dispensing step is desirable, but the final product produced by single dispensing techniques in the past have problems. Referring to
FIG. 1
, which depicts a final product obtained through the use of a single dispensing step, the package assembly
10
includes an organic package
12
to which a semiconductor die
14
is attached, either through a ball grid array
16
or a pin grid array
16
. Underfill
18
has been dispensed in the gap between the semiconductor die
14
and the package
12
. The dispensing of the underfill
18
is typically performed at a single one of the four sides on the semiconductor die
14
. An “ideal weight” of underfill is normally dispensed. The ideal weight of the underfill
18
is determined based upon the volume of the gap between the semiconductor die
14
and the package
12
. Hence, the volume is the square area of the semiconductor die
14
multiplied by the height of the gap between the semiconductor die
14
and the package
12
.
Dispensing the underfill
18
at one side of the semiconductor die
14
creates a build-up of the underfill
18
at that side, forming a fillet
20
that substantially completely covers the side of the semiconductor die
14
at the dispensing side. Therefore, there is very little exposed surface
24
on that particular side. The fillets
22
on the other three sides of the semiconductor die
14
, as depicted in
FIG. 1
, provide much less coverage of the other three sides. Exposed surface
26
is thus significantly larger than the exposed surface
24
.
The imbalance in coverage of the sides of the semiconductor die
14
leads to unreliability in the solder joints. When the package assembly
10
undergoes thermal stress, delamination may occur since the semiconductor die
14
is not held as equally securely on the two opposing sides of the semiconductor die
14
. In other words, when two opposing sides have very different sized exposed surfaces
24
,
26
, this imbalance of fillet coverage allows the semiconductor die
14
connection to be torqued in response to thermal stress. This leads to unreliability of the solder joint connections.
Hence, there is a problem in providing sufficient underfill on all four sides of a semiconductor die to assure solder joint reliability, but at the same time avoid extra processing steps and other unworkable solutions to form fillets and provide solder joint reliability.
SUMMARY OF THE INVENTION
These and other needs are met by embodiments of the present invention which provide a method for forming a package assembly, comprising the steps of attaching a semiconductor die to a package with a gap formed therebetween. Underfill is dispensed in a single step at a side of the semiconductor die and forms fillets. The semiconductor die has two pairs of opposing sides with a height H. The fillets cover at least 0.15H of each of the sides. The fillet coverage imbalance for the opposing sides of the respective pairs is less than 30%.
The inventors have determined that adequate solder joint reliability is achieved when the fillet coverage imbalance for each of the pairs of the opposing sides of the semiconductor die is less than 30%. Full fillet coverage (i.e. 100% coverage) of the sides of the semiconductor die is not necessary to provide solder joint reliability. However, the inventors have recognized that the avoidance of torque created by the thermal stress and excessive fillet coverage imbalance needs to be avoided. Also, the inventors have determined that coverage of at least 15% of each of the sides on the semiconductor die is necessary to achieve solder joint reliability.
In preferred embodiments of the invention, the ideal weight of underfill is determined, and the amount of underfill dispensed is equal to between 1.10 to 1.30 of the ideal weight of the underfill. This range of dispensing amount assures that the fillet coverage imbalance is less than 30% on the opposing sides of the respective pairs of the semiconductor die sides and that the fillets cover at least 0.15 of the height of the each of the sides of the semiconductor die.
The earlier stated needs are also met by an embodiment of the present invention which provides a method of forming a reliable laminate flip-chip assembly having a die and a package, and includes the steps of attaching the die to the package, a gap being formed between the die and the package, the gap having a volume. The method also includes determining the ideal weight W of underfill based on the volume; and dispensing underfill at one side of the die, the weight of underfill dispensed being between 1.1W to 1.3W.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4890152 (1989-12-01), Hirata et al.
patent: 5889332 (1999-03-01), Lawson et al.
patent: 6074895 (2000-06-01), Dery et al.
patent: 6150724 (2000-11-01), Wenzel et al.
Derwent Abstracted Publication No. JP10209206A “Semiconductor device manufacturing method . . . height of flip chip.” Nippondenso Co. Ltd. Aug. 7, 1998. (Abstract Only).*
Japanese Abstacted Application No. JP08175153. “Resin method for transferring bumps in flip chip mounting”

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