Method of fabricating recessed gate static induction transistors

Details Method of fabricating recessed gate static induction transistors Method of fabricating recessed gate static induction transistors

1986-05-02

1987-12-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 6, 437200, 437 41, 437911, 357 22, H01L 21283, H01L 21265

Patent

active

047133589

ABSTRACT:
A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. Parallel grooves are etched through the low resistivity N-type layer into the high resistivity N-type layer forming interposed ridges of silicon. When fabricating junction gate devices, P-type zones are formed at the end walls of the grooves by ion implantation. A layer of silicon oxide is formed on the side walls of the grooves exposing the silicon at the end walls of the grooves and at the surfaces of the ridges. A layer of a silicide-forming metal, specifically cobalt, is deposited. A rapid thermal annealing treatment is performed which causes the cobalt to react with the silicon and form cobalt silicide at the cobalt-silicon interfaces. The cobalt does not react with the silicon oxide at the side walls of the grooves. The unreacted cobalt is removed by an etching solution which does not attack the cobalt silicide. Metal layers are placed on the cobalt silicide to increase its conductivity as contact members.

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