Etching a substrate: processes – Forming or treating thermal ink jet article
Reexamination Certificate
2007-02-13
2007-02-13
Hassanzadeh, Parviz (Department: 1763)
Etching a substrate: processes
Forming or treating thermal ink jet article
C029S890100
Reexamination Certificate
active
11071471
ABSTRACT:
A method of fabricating a printhead integrated circuit to incorporate a plurality of nozzle arrangements is provided. Each nozzle arrangement has nozzle chamber walls defining a nozzle chamber and an ink ejection port bounded by a rim. The method comprises providing a substrate having drive circuitry formed thereon, depositing a sacrificial material layer on the substrate, etching the sacrificial material layer to define deposition zones for the nozzle chamber walls and the rim, depositing a conformal layer of structural material on the sacrificial layer, planarizing the conformal layer to a predetermined depth to define each ink ejection port bounded by its respective rim and etching away the sacrificial material layer. The sacrificial material has a coefficient of thermal expansion substantially the same as that of the substrate.
REFERENCES:
patent: 5126768 (1992-06-01), Nozawa et al.
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5479197 (1995-12-01), Fujikawa et al.
patent: 5790151 (1998-08-01), Mills
patent: 6022099 (2000-02-01), Chwalek et al.
patent: 6260963 (2001-07-01), Reistad et al.
patent: 6273544 (2001-08-01), Silverbrook
patent: 6294420 (2001-09-01), Tsu et al.
patent: 7052114 (2006-05-01), Silverbrook
patent: 2004/0008237 (2004-01-01), Silverbrook
patent: 0539804 (1993-05-01), None
patent: 829360 (1998-03-01), None
patent: 0865922 (1998-09-01), None
patent: 867294 (1998-09-01), None
patent: 2086807 (1982-05-01), None
patent: 2333065 (1982-05-01), None
patent: 0764977 (1997-03-01), None
patent: 2986807 (1999-07-01), None
U.S. Appl. No. 09/835,472, filed Oct. 15, 1999, Silverbrook.
U.S. Appl. No. 09/807,297, filed Oct. 15, 1999, Silverbrook.
Culbert Roberts
Hassanzadeh Parviz
Silverbrook Research Pty Ltd
LandOfFree
Method of fabricating printhead IC using CTE matched wafer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating printhead IC using CTE matched wafer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating printhead IC using CTE matched wafer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3862184