Method of fabricating polysilicon/silicon junction field effect

Details Method of fabricating polysilicon/silicon junction field effect Method of fabricating polysilicon/silicon junction field effect

1980-05-06

1982-06-08

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148187, 357 22, H01L 2122

Patent

active

043332242

ABSTRACT:
A junction field effect transistor is fabricated in crystalline silicon by using oppositely doped polysilicon as the gate (POSFET). The depletion region of the pn (or np) junction formed at the polysilicon/silicon interface is used as the gate electrode to modulate the current path through the silicon channel from source to drain, the source and drain contacts may either be conventional metal or polysilicon heavily doped of the same conductivity type as the single crystal silicon substrate.

REFERENCES:
patent: 3804681 (1974-04-01), Drangeid et al.
patent: 3859716 (1975-01-01), Tihanyi
patent: 3897625 (1975-08-01), Tihanyi et al.
patent: 4170818 (1979-10-01), Tobey et al.
patent: 4277883 (1981-07-01), Kaplan

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