Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-12-18
2004-01-27
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S611000, C438S613000
Reexamination Certificate
active
06682956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a package having metal runner and, more particularly, to a metal runner fabrication method to prevent splits of a solder mask due to differences of thermal strain between the metal runner and the solder mask.
2. Description of the Related Art
A chip size package, in which more than 80% of the whole package size is occupied by a semiconductor chip, has been developed in various fields since it has advantages of small size and light weight. In the chip size package, a greater number of packages than in a conventional semiconductor package are packaged on the same printed circuit boards. Therefore, chip size packages are applied to high performance electric and electronic products.
Generally, a pad rearrangement process is required to fabricate the chip size package. The pad arrangement is a process whereby a bonding pad of semiconductor chip is rearranged in a predetermined position. In a conventional method, a metal runner is formed for the pad rearrangement. The metal runner is generally made of copper or aluminum.
The pad rearrangement process is performed in fabrications of chip size packages, ball grid array packages and wafer level packages.
FIG. 1
is a drawing showing a conventional chip size package having a metal runner. As shown in
FIG. 1
, a stress buffer layer
3
is formed on a semiconductor chip to expose the bonding pads (not shown) and a metal runner
5
a
is formed on the stress buffer layer
3
. The metal runner
5
a
is made of copper and connected to each bonding pad (not shown). On the stress buffer layer
3
and the metal runner
5
a,
a solder mask
6
, made of a polymer such as Benzo Cyclo Butyne (BCB), is formed to expose a ball land
5
b
of the metal runner
5
a.
On the exposed ball land
5
b,
a solder ball
7
is formed.
FIGS. 2A
to
2
E are cross-sectional views taken along line II-II′ of
FIG. 1
to show a method of forming the above-mentioned conventional package.
Referring to
FIG. 2A
, a stress buffer layer
3
is formed on a semiconductor chip
1
to expose the bonding pads (not shown). Negative type photoresist
4
is applied on the stress buffer layer
3
and then, the photoresist
4
is exposed by using an exposure mask
10
. Subsequently, as shown in
FIG. 2B
, a photoresist pattern
4
a
is formed which has a rectangular cross section and defines a metal runner formative region.
Referring to
FIG. 2C
, a copper layer
5
is formed to have a height similar to the photoresist pattern
4
a
by using a plating process on the metal runner formative region defined by the photoresist pattern
4
a.
Then, as shown in FIG._
2
D, the photoresist pattern
4
a
is removed, thereby forming metal runners
5
a
having a rectangular cross section and being in contact with each bonding pad of the semiconductor chip
1
on the stress buffer layer
3
.
Referring to
FIG. 2E
, a solder mask
6
, made of a polymer such as BCB, is formed to expose a ball land (not shown) of the metal runner
5
a
on the stress buffer layer
3
and the metal runner
5
a.
Thereafter, although it is not shown in the drawings, a solder ball is adhered on the exposed ball land of the metal runner
5
a,
thereby completing the chip size package.
However, according to the conventional chip size package having a metal runner, when thermal load is applied from the outside into the package during temperature cycle test, thermal strain differences are generated between the metal runner and the solder mask comprising polymer such as BCB, whereby stresses are concentrated on each corner of the metal runner, marked as stress concentration points
1
and
2
. As a result, splits are generated on the solder mask.
When the solder mask has a thickness much thicker than that of the metal runner, the splits of solder mask are not generated by the stress concentration. However, it is still impossible to prevent generation of splits in solder mask since the solder mask is formed by a spin coating process and it is difficult to coat thickly. Even when a thick solder mask is formed, folds are generated and it is difficult to perform a patterning process after exposure. Therefore, according to the conventional method, the solder mask and the metal runner have a thickness of approximately 10 to 15 &mgr;m and 10 &mgr;m, respectively.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and an object of the present invention is to provide a method of fabricating a package having metal runner while preventing generation of splits in the solder mask due to stress concentration.
In order to accomplish the above object, the present invention comprises steps of: forming a stress buffer layer on a semiconductor chip having a plurality of bonding pads to expose the bond pad; applying negative type photoresist on the stress buffer layer; exposing and developing the photoresist to form a photoresist pattern having a convex cross section and defining a metal runner formative region; forming a metal layer having a height approximately equal to that of the photoresist pattern on the metal runner formative region; removing the photoresist pattern to form metal runner being in contact with the bonding pad of the semiconductor chip and having a concave cross section; forming a solder mask exposing a ball land of the metal runner on the stress buffer layer including the metal runners; and adhering a solder ball on the exposed ball land.
The present invention also comprises steps of forming a stress buffer layer on a semiconductor chip having a plurality of bonding pads to expose the bonding pad; applying a first photoresist of negative type on the stress buffer layer; forming a first photoresist pattern having an inverse trapezoidal cross section by exposing and developing the first photoresist; forming a first metal layer in spaces formed by the first photoresist pattern; applying a second photoresist on the first photoresist pattern and on the first metal layer; forming a second photoresist pattern exposing the first metal layer and having a trapezoidal cross section by exposing and developing the second photoresist; forming a second metal layer on the exposed first metal layer; removing the second and the first photoresist pattern to form a metal runner being in contact with the bonding pad of the semiconductor chip and having a concave cross section; forming a solder mask on the stress buffer layer including the metal runners to expose a ball land of the metal runner; and adhering a solder ball on the exposed ball land.
Moreover, the present invention may also comprise steps of forming a stress buffer layer on a semiconductor chip having a plurality of bonding pads to expose the bonding pad; stacking negative type photoresist tapes having different etching speeds, wherein etching speeds of upper and lower tapes are higher than that of a center tape, on the stress buffer layer; forming a photoresist pattern having a convex cross section and defining a metal runner formative region by exposing and developing the photoresist tapes; forming a metal layer on the metal runner formative region; removing the photoresist pattern to form metal runners being in contact with each bonding pad of the semiconductor chip and having a concave cross section; forming a solder mask on the stress buffer layer including the metal runners to expose a ball land of the metal runner; and adhering a solder ball on the exposed ball land.
The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.
REFERENCES:
patent: 6236112 (2001-05-01), Horiuchi et al.
patent: 6455408 (2002-09-01), Hwang et al.
Everhart Caridad
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Luu Chuong A
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