Method of fabricating openings and contact holes

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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Details

C438S243000, C438S639000, C438S743000

Reexamination Certificate

active

07825034

ABSTRACT:
A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.

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patent: 2004/0018712 (2004-01-01), Plas et al.
patent: 2004/0169224 (2004-09-01), Ebihara
patent: 2005/0074965 (2005-04-01), Lee et al.
patent: 1337740 (2002-02-01), None
patent: 1519953 (2004-08-01), None

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