Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Patent
1998-03-05
2000-09-19
Fourson, George
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
438264, 438265, H01L 218247
Patent
active
061210722
ABSTRACT:
A method of fabricating a nonvolatile memory device having a substrate, includes the steps of forming a plurality of bit lines in the substrate, forming a plurality of field oxide layers on the substrate perpendicular to the bit lines, forming a gate insulating layer on an entire surface of the substrate including the bit lines and the field oxide layers, forming a plurality of floating lines on the gate insulating layer between the bit lines, forming a dielectric layer on the entire surface of the semiconductor substrate including the floating line's and the gate insulating layer, forming a plurality of word lines between the field oxide layer perpendicular to the bit lines, forming sidewall spacer at both sides of the word lines, selectively removing the dielectric layer and the floating lines using the word lines and the sidewall spacer as masks to form a plurality of floating gates, forming a tunneling layer at both sides of the floating gates, and forming a plurality of program lines between the bit lines.
REFERENCES:
patent: 4267632 (1981-05-01), Shappir
patent: 5707897 (1998-01-01), Lee et al.
Hitoshi Kume, et al., "A 1.28 .mu.m.sup.2 Contactless Memory Cell Technology for a 3V-Only 64 Mbit EEPROM"; International Electron Devices meeting 1992, Technical Digest; pp. 24.7.1-27.7.3; Dec. 13-16, 1992.
Choi Woong-Lim
Ra Kyeong-Man
Fourson George
LG Semicon Co. Ltd.
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