Method of fabricating non-volatile ferroelectric transistors

Details Method of fabricating non-volatile ferroelectric transistors Method of fabricating non-volatile ferroelectric transistors

2003-03-24

2004-07-13

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S201000, C438S211000

Reexamination Certificate

active

06762063

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to ferroelectric non-volatile integrated circuits, and specifically to a simplified fabrication technique which minimizes etching-induced ferroelectric stack damage.
BACKGROUND OF THE INVENTION
A gate stack of a state-of-the-art ferroelectric (FE) memory transistor includes formation of a self-aligned FE stack, which includes deposition and etching of a top electrode material, the ferroelectric material, and a bottom electrode material. There are some serious problems associated with state-of-the-art techniques, which result in a less than desirable yield, such as re-deposition of etched and masking material on the structure, usually as a result of etching the top electrode material, the FE material and the bottom electrode material to form the FE self-aligned stack. Additionally, plasma etching of the FE material may damage the non-volatile properties of the material, which property cannot be restored completely.
SUMMARY OF THE INVENTION
A method of fabricating a non-volatile ferroelectric memory transistor includes preparing a silicon substrate, including forming an active region on the substrate; implanting ions to form a source region and a drain region in the active region; forming a bottom electrode; depositing a ferroelectric layer over the active region; depositing a top electrode; depositing an insulating oxide layer over the active region; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode.
A non-volatile ferroelectric memory transistor includes a silicon substrate having an active region formed thereon; a source region and a drain region formed about a gate region in the active region; a bottom electrode formed above the gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; a top electrode formed on the ferroelectric layer; an insulating oxide layer; and a source electrode, a gate electrode and a drain electrode.
An object of the invention is to fabricate a ferroelectric non-volatile memory transistor which does not require gate stack etching.
A further object of the invention is to fabricate a ferroelectric non-volatile memory transistor with minimal etching-induced damage.
Another object of the invention is to provide a fabrication process for a ferroelectric non-volatile memory transistor which is less complex than prior art techniques.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.


REFERENCES:
patent: 6011285 (2000-01-01), Hsu et al.
patent: 6194752 (2001-02-01), Ogasahara et al.

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