Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1999-07-20
2000-11-21
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438710, 438712, 438719, H01L 218242
Patent
active
061502782
ABSTRACT:
An improved method of fabricating a node capacitor for a dynamic random access memory (DRAM) process is disclosed. The process includes depositing a first interpoly dielectric (IPD1) layer over a substrate, patterning a first photoresist layer on the first interpoly dielectric layer, thereby defining a trench. A trench is etched in the first interpoly dielectric layer using the first photoresist layer as a mask. A first polysilicon layer is deposited on the first interpoly dielectric layer. The first polysilicon layer is etched to expose the first interpoly dielectric layer, then forming a landing pad over the substrate. In order to a polycide layer and a second interpoly dielectric (IPD2) layer are deposited, patterning a second photoresist layer, thereby defining a bit line structure. A bit line structure is formed, then depositing a spacer on the bit line structure. A second polysilicon layer is deposited, patterning a third photoresist layer, thereby defining a bottom electrode. A bottom electrode is formed, then depositing a thin NO (silicon nitride-silicon oxide) dielectric layer on the bottom electrode. An addition step is performed before forming the thin NO dielectric layer on the bottom electrode. In this additional step, a hemispherical grain (HSG) polysilicon layer is formed on the second polysilicon layer. This advantage is used to the hemispherical grain polysilicon layer increasing the area of a node capacitor. A third polysilicon layer is deposited completely covering the thin NO dielectric layer to form a top electrode.
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Lin Kun-Chi
Tan Wayne
United Microelectronics Corp.
Utech Benjamin L.
Vinh Lan
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