Method of fabricating nano-scale resistance cross-point...

Details Method of fabricating nano-scale resistance cross-point... Method of fabricating nano-scale resistance cross-point...

2006-11-28

2006-11-28

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Resistor

C438S003000, C438S238000

Reexamination Certificate

active

07141481

ABSTRACT:
A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

REFERENCES:
patent: 4983534 (1991-01-01), Kikuta
patent: 6507466 (2003-01-01), Hayashi et al.
patent: 6569745 (2003-05-01), Hsu
patent: 2001/0035545 (2001-11-01), Schuster-Woldan et al.

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