Metal working – Method of mechanical manufacture – Electrical device making
Patent
1983-02-14
1985-09-24
Hearn, Brian E.
Metal working
Method of mechanical manufacture
Electrical device making
29571, 29591, 148 15, 148188, 148190, 148176, H01L 21225
Patent
active
045425809
ABSTRACT:
Disclosed are improved bipolar and field effect transistors having n-type silicon regions and associated electrical contacts comprising monocrystalline silicon doped with arsenic and phosphorus. The transistors are fabricated by depositing on a silicon substrate a coating of amorphous silicon comprising a first layer heavily doped with phosphorus and a second layer below the first doped with arsenic. Energy is selectively applied to melt the coating. As the coating resolidifies and cools, arsenic diffuses into the substrate to form shallow n-type regions which are annealed by heat from the coating. Heavily phosphorus-doped, conductive monocrystalline silicon forms above the n-type regions on the substrate, whereas polycrystalline silicon forms above dielectric or other materials. Selective removal of the polysilicon yields shallow, annealed n-type regions integral with self-registered contacts. The resulting transistors have low RC time constants and low contact resistance.
REFERENCES:
patent: 3620814 (1971-11-01), Clark et al.
patent: 3912557 (1975-10-01), Hochberg
patent: 3915765 (1975-10-01), Cho et al.
patent: 3957474 (1976-05-01), Kobayashi et al.
patent: 3965385 (1976-06-01), Feist et al.
patent: 4041518 (1977-08-01), Shemizu et al.
patent: 4042006 (1977-08-01), Engl et al.
patent: 4214918 (1980-07-01), Gat et al.
patent: 4249141 (1981-02-01), Brown et al.
patent: 4249968 (1981-02-01), Gardiner et al.
patent: 4260649 (1981-04-01), Dension et al.
patent: 4292091 (1981-09-01), Togei
patent: 4318752 (1982-03-01), Tien
patent: 4319954 (1982-03-01), White et al.
patent: 4322253 (1982-03-01), Pankoue et al.
patent: 4340617 (1982-07-01), Deutsch et al.
patent: 4400715 (1983-08-01), Barbee et al.
Influence of AsH.sub.3, PH.sub.3, and B.sub.2 H.sub.6 on . . . , J. Electrochem. Soc., Solid State Science and Technology, Jan., 1973, pp. 106-109.
In-Process Thickness Monitor for Polycrystalline Silicon Deposition, J. Elec. Soc., Solid-State Sci. & Tech., Jan., 1972, pp. 112-114.
Diffusion of Impurities in Polycrystalline Silicon, J. Appl. Phys., vol. 43, No. 1, Jan. 1972, pp. 83-91.
Laser-Induced Vapor Deposition of Silicon, Applied Pysics Letter (35) 8, Oct. 15, 1979, pp. 626-627.
Flash Evaporation of Compounds with a Pulsed-Discharge CO.sub.2 Laser, Applied Optics, May 1976, vol. 15, No. 5, pp. 1327-1330.
Effect of Emitter Contact on Curent Gain of Silicon Bipolar Devices, IEEE Transactions on Electron Devices, vol. Ed-27, No. 11, 11/80, pp. 2051-2055.
Auyang Hunter L.
Hearn Brian E.
Prime Computer Inc.
LandOfFree
Method of fabricating n-type silicon regions and associated cont does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating n-type silicon regions and associated cont, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating n-type silicon regions and associated cont will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1608215