Electrical resistors – Resistance value responsive to a condition – Current and/or voltage
Reexamination Certificate
2000-08-22
2001-05-15
Gellner, Michael L. (Department: 2832)
Electrical resistors
Resistance value responsive to a condition
Current and/or voltage
C338S020000, C338S307000, C338S309000, C029S610100, C029S619000
Reexamination Certificate
active
06232867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating monolithic chip varistors and to monolithic chip varistors. More particularly, the invention relates to improvements in a method of forming external electrodes in a monolithic chip varistor.
2. Description of the Related Art
A monolithic chip varistor is generally provided with a varistor body including a plurality of varistor layers composed of a zinc oxide-based ceramic material and at least one pair of internal electrodes opposed to each other with one of the varistor layers therebetween, and a pair of external electrodes, each formed on a specific portion of the external surface of the varistor body. Each external electrode is electrically connected to either one of the internal electrodes opposed to each other with a specific varistor layer therebetween.
In the monolithic chip varistor as described above, the external electrode typically includes a plurality of layers composed of different materials, and an outermost layer thereof, which is composed of a metal film having satisfactory solderability so as to impart satisfactory solderability to the external electrode. Such a metal film having satisfactory solderability is usually formed by electroplating.
A conventional technique, which is of interest in the present invention, concerning a monolithic ceramic electronic component provided with external electrodes as described above is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 8-97072.
The above publication describes a method in which a first external electrode layer containing glass frit is formed on each end face of an electronic component body composed of a ceramic so as to be electrically connected to internal electrodes, and a second external electrode layer without containing glass frit is formed thereon, and then an outermost layer is formed by electroplating.
However, if the method disclosed in Japanese Unexamined Patent Application Publication No. 8-97072 is used in forming external electrodes on a varistor body provided with varistor layers composed of a zinc oxide-based ceramic material, since the zinc oxide-based ceramic material has relatively low electrical resistance, a potential difference between the external electrode, for example, the second layer, and the exposed surface of the varistor body becomes relatively small. Therefore, when electroplating is performed, the exposed surface of the varistor body is reduced and a plating film may be formed both on the external surface of the varistor body and on the second layer, resulting in degradation in the characteristics of the monolithic chip varistor.
Since the zinc oxide-based ceramic material is also easily affected by acids or alkalis, when the exposed surface of the varistor body is brought into contact with a plating solution during electroplating, dissolution occurs, resulting in deterioration of the varistor body, and it becomes difficult to maintain the varistor characteristics.
Furthermore, since the outermost layer for the external electrode is formed when electroplating is performed, internal defects easily occur in the varistor body, which may also result in degradation in the characteristics of the monolithic chip varistor. The problem is believed to be caused by the plating solution penetrating into the varistor body through a space between the external electrode and the varistor body, etc. The penetration of the plating solution at a section where the internal electrodes are located particularly causes a more serious problem, such as deterioration of the joint between the internal electrodes and the varistor layers, resulting in degradation in the characteristics of the monolithic chip varistor, particularly, in a life test.
The problem due to the contact between the exposed surface of the varistor body and the plating solution can be solved to a certain extent by covering the exposed surface of the varistor body with a glass film, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 8-153607.
However, it is relatively difficult to form a glass film only on the exposed surface of the varistor body with high accuracy. For example, the glass film may also be formed on the external electrode portion, or the exposed surface maybe insufficiently covered with the glass film. In the former case, the formation of the outermost plating layer is blocked, and in the latter case, the problems associated with a case when such a glass film is not formed cannot be overcome completely.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating a monolithic chip varistor and a structure of a monolithic chip varistor obtained by the same method, in which the problems described above can be solved.
In accordance with the present invention, a method of fabricating a monolithic chip varistor includes the steps of preparing a varistor body including a plurality of varistor layers composed of a zinc oxide-based ceramic material and at least one pair of internal electrodes opposed to each other with one of the varistor layers therebetween;
forming a first layer for each of a pair of external electrodes by applying a metal component and a glass component to respective exterior portions of the varistor body so as to be electrically connected to a specific internal electrode, followed by heat treatment;
forming a second layer for the external electrode on the first layer by applying a glass component, followed by heat treatment;
forming a third layer for the external electrode on the second layer by applying a glass component that is different from the glass component used for forming the second layer, followed by heat treatment;
forming a fourth layer for the external electrode on the third layer by applying a metal component that is different from the metal component used for forming the first, followed by heat treatment under the same heat treatment conditions as those used for the formation of the first layer; and
forming a fifth layer for the external electrode by forming an electroplating layer composed of a metal having satisfactory solderability.
During the heat treatment for forming the fourth layer, the metal component contained in the fourth layer is diffused into the second layer and the third layer.
Preferably, in the step of forming the first layer, the amount of the glass component is set at 5% to 10% by weight relative to the metal component.
And, preferably, in the step of forming the fourth layer, the amount of the glass component is set at less than 5% by weight relative to the metal component.
Preferably, simultaneously with the formation of the second layer, a first insulating layer composed of the glass component contained in the second layer is formed on the surface of the varistor body exposed from the first layer, and simultaneously with the formation of the third layer, a second insulating layer composed of the glass component contained in the third layer is formed on the first insulating layer.
The present invention is also directed to a structure of a monolithic chip varistor fabricated by the method described above.
More specifically, in accordance with the present invention, a monolithic chip varistor is provided with a varistor body including a plurality of varistor layers composed of a zinc oxide-based ceramic material and at least one pair of internal electrodes opposed to each other with one of the varistor layers therebetween, and a pair of external electrodes, each formed on an exterior portion of the varistor body. Each external electrode is electrically connected to either one of the internal electrodes opposed to each other with a specific varistor layer therebetween.
Each external electrode includes a first layer formed on the exterior portion of the varistor body and electrically connected to the internal electrodes, a second layer formed on the first layer, a third layer formed on the second layer, a fourth layer formed on the third layer, and a f
Morimoto Tadashi
Tominaga Toru
Yoshida Yoshikazu
Gellner Michael L.
Lee Richard K.
Murata Manufacturing Co. Ltd.
Ostrolenk Faber Gerb & Soffen, LLP
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