Method of fabricating MIM capacitor

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

Reexamination Certificate

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Details

C438S240000, C438S253000, C257S306000, C257S309000, C257SE29346, C257SE25014

Reexamination Certificate

active

11027838

ABSTRACT:
A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.

REFERENCES:
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patent: 6387775 (2002-05-01), Jang et al.
patent: 6410381 (2002-06-01), Kim et al.
patent: 6528366 (2003-03-01), Tu et al.
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patent: 6794702 (2004-09-01), Park
patent: 6916722 (2005-07-01), Huang et al.
patent: 6982472 (2006-01-01), Kiyotoshi
patent: 7002201 (2006-02-01), Yasuda
patent: 2002/0163029 (2002-11-01), Dirnecker et al.

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