Method of fabricating memory device using a halogen implant

Details Method of fabricating memory device using a halogen implant Method of fabricating memory device using a halogen implant

1994-05-17

1996-11-19

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 52, 437 58, 437979, 437238, 148DIG163, 148DIG116, 148DIG117, H01L 2131, H01L 218239

Patent

active

055762263

ABSTRACT:
A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.

REFERENCES:
patent: 4240096 (1980-12-01), Hiraki et al.
patent: 4420872 (1983-12-01), Solo de Zalvidav
patent: 4627153 (1986-12-01), Masuoka
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4669178 (1987-06-01), Johnson
patent: 4743563 (1988-05-01), Pfiester et al.
patent: 4748131 (1988-05-01), Zietlow
patent: 4748134 (1988-05-01), Holland et al.
patent: 4920076 (1990-04-01), Holland et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5106768 (1992-03-01), Kuo
patent: 5108935 (1992-04-01), Rodder
patent: 5215934 (1993-06-01), Tzeng
patent: 5254489 (1993-10-01), Nakata
patent: 5330920 (1994-07-01), Soleimani et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5372951 (1994-12-01), Anjum et al.
patent: 5426065 (1995-06-01), Chan et al.
patent: 5432114 (1995-07-01), O
Translation of JP 4-100336 (Takeda).
G. Greeuw et al., Sol. St. Electron., 26, 3 (1983) 241 ". . . Silicon By Halogen implantation".
P. J. Wright et al., IEEE Trans. Electron. Dev., 36, 5 (1989) 879 ". . . F in SiO2 Gate Dielectrics", whole paper.
N. Kaasai, et al., IEEE Trans. Electron Dev., 37, 6 (1990) 1426 ". . . F incorporated nMOSFET's".
S. Wolf, "Silicon Processing for the VLSI Era" vol. II, 1992, pp. 572-580.
J. C. Hseih et al., IEEE Electon Dev. Lett., 14 (1993) 222 ". . . BF.sub.2 or B implanted poly-Si Gate . . . POC1.sub.3. . . ".
P. J. Wright et al., IEEE Trans on Electron Dev., 36 (1989) 879, "F in SiO.sub.2 Gate Dielectrics" (Abs. only).

Affiliated with

Also associated with

Rating

Method of fabricating memory device using a halogen implant does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating memory device using a halogen implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating memory device using a halogen implant will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-540489