Fishing – trapping – and vermin destroying
Patent
1996-02-12
1996-12-17
Tsai, Jey
Fishing, trapping, and vermin destroying
437 52, 437 45, H01L 21265
Patent
active
055852963
ABSTRACT:
A method of fabricating memory cells with buried bit lines. In this method, a pad oxide layer is formed on a first conductivity-type silicon substrate. A photoresist layer is formed on the pad oxide layer while exposing predetermined areas of channels. A thick oxide layer is deposited by liquid phase deposition (LPD). The photoresist layer is removed. Second conductivity-type impurities are implanted to form source-drain electrodes using the thick oxide layer as a mask. The thick oxide layer and the pad oxide layer are removed to form bit lines and then word lines are formed crossing the bit lines, whereby the structure with buried bit lines and an array of memory cells is completed.
REFERENCES:
patent: 5436185 (1995-07-01), Hsue et al.
patent: 5504030 (1996-04-01), Chung et al.
patent: 5525535 (1996-06-01), Hong
patent: 5536669 (1996-07-01), Su et al.
Chia Belle
Chung Cheng-Hui
Sheng Yi-Chung
Tsai Jey
United Microelectronics Corporation
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