Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-09-28
2001-01-16
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S399000, C438S638000
Reexamination Certificate
active
06174782
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88110421, filed Jun. 22, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a DRAM capacitor. More particularly, the present invention relates to a method for fabricating a lower electrode of the capacitor.
2. Description of Related Art
FIGS. 1A
to
1
C are schematic, cross-sectional diagrams showing the fabrication steps of a lower electrode of a capacitor, while
FIGS. 2A
to
2
C are schematic, cross-sectional diagrams taken at right angle to the first cross-sectional views and bisecting at a line II—II in
FIGS. 1A
to
1
C.
Referring to FIG.
1
A and
FIG. 2A
, a substrate
100
is provided with isolation structures formed therein. A gate
111
is then formed on the substrate
100
, wherein the gate
111
is constituted by stacking a gate oxide layer
108
, a conducting layer such as a polysilicon layer or a tungsten silicide layer, and a cap layer
112
in sequence on the substrate
100
. A spacer
114
is formed on a sidewall of the gate
111
before forming a source/drain (S/D) region by doping in the substrate
100
. Landing pads
106
a
and
106
b
are formed to couple with the S/D region. A patterned first dielectric layer
102
is formed to cover, a part of the landing pads
106
a,
106
b,
the exposed cap layer
112
, and the substrate
100
.
Further referring to FIG.
1
A and
FIG. 2A
, a bit line
116
is formed to cover the landing pad
106
a
and a part of the dielectric layer
102
before forming a second dielectric layer
104
on the first dielectric layer
102
. An etching step is performed to form a contact opening
118
, which extends through the second dielectric layer
104
and the first dielectric layer
102
to expose the landing pads
106
b.
Referring to FIG.
1
B and
FIG. 2B
, a doped polysilicon layer
120
is formed to fill the contact opening
118
and covers the second dielectric layer
104
.
Referring to FIG.
1
C and
FIG. 2C
, the doped polysilicon layer
120
is patterned to form a first storage node
120
a
and a second storage node
120
b,
which serve as lower electrodes of a capacitor.
The contact opening
118
formed by the conventional process may easily expose the bit line when a misalignment occurs during the contact formation. As a result, a doped polysilicon layer that is subsequently deposited in the contact opening makes contact with the exposed bit line, leading to an electrical short circuit and a damage to the semiconductor device.
With the increased integration for the integrated circuit, the problem mentioned above gets worse as a gap width between the sidewall of the contact opening and the bit line has gradually decreased to, for example about 0.05 microns. One solution for above problem is to increase the gap width between the sidewall of the contact opening and the bit line. An increase in gap width is commonly achieved by decreasing the size of the contact opening. Since the contact opening manufactured by photolithography has a size limitation, only the narrow gap is formed as a consequence. If the gap between the contact and the bit line is too narrow, the doped polysilicon layer that fills the contact opening may form an unnecessary contact with the bit lines when misalignment occurs, leading to the electrical short circuit.
Conventionally, an increase in the storage charge of the capacitor is achieved by increasing the surface area of a lower electrode. So, a thicker doped polysilicon layer is usually formed for manufacturing the lower electrode. As there is a very small gap in between two adjacent capacitors, it is not easy to completely etch through the thicker doped polysilicon layer for separating two adjacent capacitors, due to a large aspect ratio of the thick doped polysilicon layer.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a lower electrode of a capacitor, which method provides a substrate, on which forms landing pads and gates, wherein the landing pads are connected to a source/drain region of the substrate. A first dielectric layer is formed to cover the landing pads and the gates and is patterned to form an opening. The opening is filled with a bit line, before forming a second dielectric layer which cover the bit line and the first dielectric layer. A stop layer, an insulating layer, and a mask layer are formed in sequence on the second dielectric layer. The insulating layer and the mask layer are patterned to form a capacitor opening that exposes the stop layer, followed by forming a spacer on a sidewall of the capacitor opening. With the patterned mask layer and the spacer serving as an etching mask, the stop layer, the second dielectric layer and the first dielectric layer are etched in sequence to form a node contact opening which exposes the landing pad. The capacitor opening and the node contact opening form a damascene contact opening, while the damascene contact opening is filled with a conformal conducting layer. The conducting layer is then planarized by chemical mechanical polishing (CMP) to form two separate storage capacitors.
As embodied and broadly described herein, the invention provides a spacer that overcomes the size limitation imposed by using photolithography, so that the bit line is not exposed by the damascene contact opening described above. Also, the conducting layer is planarized by CMP to form the storage capacitors, so use of mask for photolithography is reduced in the invention. Thus, the steps involved in the process are simplified and the process cost is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5753547 (1998-05-01), Ying
patent: 5854119 (1998-12-01), Wu et al.
patent: 5981334 (1999-11-01), Chien et al.
patent: 5989954 (1999-11-01), Lee et al.
patent: 5998257 (1999-12-01), Lane et al.
Nguyen Tuan H.
Thomas Kayden Horstemeyer & Risley, L.L.P.
United Microelectronics Corp.
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