Method of fabricating low-power CMOS device

Details Method of fabricating low-power CMOS device Method of fabricating low-power CMOS device

2008-05-13

2008-05-13

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S401000, C438S430000, C438S431000, C438S432000, C257SE21549, C257SE21547, C257SE21572

Reexamination Certificate

active

11318433

ABSTRACT:
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.

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