Method of fabricating low-power CMOS device

Details Method of fabricating low-power CMOS device Method of fabricating low-power CMOS device

2008-05-13

2008-05-13

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S401000, C438S430000, C438S431000, C438S432000, C257SE21549, C257SE21547, C257SE21572

Reexamination Certificate

active

07371655

ABSTRACT:
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.

REFERENCES:
patent: 5895253 (1999-04-01), Akram
patent: 5920786 (1999-07-01), Pham et al.
patent: 5945352 (1999-08-01), Chen et al.
patent: 5998279 (1999-12-01), Liaw
patent: 6107159 (2000-08-01), Chuang
patent: 6187649 (2001-02-01), Gau
patent: 6214670 (2001-04-01), Shih et al.
patent: 2003/0100168 (2003-05-01), Lee et al.
patent: 2005/0054131 (2005-03-01), Wada et al.
patent: 2005/0176214 (2005-08-01), Chang et al.
patent: 2005/0191800 (2005-09-01), Wu et al.

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