Method of fabricating interconnections to I/O leads on layered e

Details Method of fabricating interconnections to I/O leads on layered e Method of fabricating interconnections to I/O leads on layered e

1989-08-16

1991-03-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437226, 437227, 437208, 437205, 357 75, 361380, H01L 2170

Patent

active

049993119

ABSTRACT:
Interconnect circuitry is formed on a selected face of several separate layered electronic assemblies simultaneously. This circuitry interconnects the I/O leads on each assembly, and it is formed by the steps of: (a) placing a plurality of the assemblies in a fixture with spacers between each assembly; (b) aligning to a single plane, one face of each assembly in the fixture on which the circuitry is to be formed; (c) mechanically squeezing the assemblies and spacers together with the fixture such that the aligned faces are held in the single plane and are exposed; (d) depositing and patterning layers of insulative and conductive materials on all of the exposed faces in the fixture; and (e) severing the layers between the faces in the space provided by the spacers. With this process, beading effects in materials that are spun onto the assemblies are eliminated; handling damage to the assemblies is eliminated; and the time and expense of processing one assembly separately is cut by several hundred percent.

REFERENCES:
patent: 4288912 (1981-09-01), Wills et al.
patent: 4313128 (1982-01-01), Schlegel et al.
patent: 4551629 (1985-11-01), Carson et al.
patent: 4704319 (1987-11-01), Belanger et al.
patent: 4706166 (1987-11-01), Go
patent: 4855809 (1989-08-01), Malhi et al.
patent: 4862249 (1989-08-01), Carlson

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