Method of fabricating interconnection structure of...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S740000, C257SE21008, C257S577000, C257S579000

Reexamination Certificate

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07112537

ABSTRACT:
A method of fabricating an interconnection structure of a semiconductor device includes the steps of successively depositing an etch-stop layer and an intermetal insulating layer on a semiconductor substrate, forming a sacrificial insulating layer on the intermetal insulating layer, forming a photoresist pattern on the sacrificial insulating layer to define a trench formation region, etching the intermetal insulating layer using a mask of the photoresist pattern to form a trench, and etching the entire etch-stop layer.

REFERENCES:
patent: 6350672 (2002-02-01), Sun
patent: 6395632 (2002-05-01), Farrar
patent: 6451683 (2002-09-01), Farrar
patent: 6534835 (2003-03-01), Farrar
patent: 6573572 (2003-06-01), Farrar
patent: 6649522 (2003-11-01), Farrar
patent: 2001-168188 (2001-06-01), None

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