Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-12-01
2008-10-21
Lebentritt, Michael S (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S393000, C438S624000, C438S761000, C257SE21260, C257SE21271
Reexamination Certificate
active
07439154
ABSTRACT:
A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.
REFERENCES:
patent: 4724021 (1988-02-01), Martin et al.
patent: 5116271 (1992-05-01), Arimoto
patent: 5260163 (1993-11-01), Nebe et al.
patent: 6753218 (2004-06-01), Devoe et al.
patent: 7291567 (2007-11-01), Tsuchiya et al.
patent: 7342315 (2008-03-01), Tsui et al.
patent: 7361992 (2008-04-01), Matsubara et al.
patent: 2007/0066028 (2007-03-01), Beyer
Chen Jei-Ming
Hsu Feng-Yu
Huang Jim-Jey
Liu Chih-Chien
Jianq Chyun IP Office
Lebentritt Michael S
United Microelectronics Corp.
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