Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2001-08-10
2004-06-15
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S221000, C205S222000
Reexamination Certificate
active
06749737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of connecting conductive layers. More particularly, the present invention relates to a method of forming inter-layer solid conductive rods applicable to a printed circuit board (PCB) and an IC carrier.
2. Description of Related Art
In addition to powerful functions, consumers now demand for lighter, thinner, smaller electronic products. Consequently, most electronic products in the market have an ever-increasing level of integration and an increasing number of powerful functions. To correspond to the increasing level of integration and functions, most printed circuit boards have a multiple of layers so that a dense array of electronic devices can be designed over the printed circuit board. An integrated circuit manufacturer not only has to reduce volume occupation of the electronic product and increase area utility, but also has to increase yield in order to reduce production cost.
FIGS. 1
a
and
1
b
are cross-sectional views of a printed circuit board showing a conventional process of forming a through hole connection between two circuit layers.
FIGS. 2
b
and
2
c
are cross-sectional views of a printed circuit board showing a conventional process of forming a blind hole connection between two circuit layers. To form a connection between two circuit layers within a printed circuit board, a hole is mechanically drilled or laser-drilled in a location where copper films
200
together with intermediate an insulating core layer
100
overlap. The hole may be a through hole
300
(as shown in
FIG. 1
a
) or a blind hole
310
(as shown in
FIG. 2
a
). A copper layer serving as a seed layer is formed on the copper films
200
and the interior walls of the hole (
300
or
310
) by an electroless plating. Thereafter, a copper electroplating is conducted to form a copper layer (as shown in
FIGS. 1
b
and
2
b
) over the seed layer. Finally, a centrally hollow conductive copper ring for connecting the electrical circuits on each side of the circuit board and acting as an inter-layer conductive medium is formed.
In the conventional method, the copper layer is formed by connecting the upper and lower conductive layer
200
to a negative electrode and performing an electroplating after the seed layer is formed. Hence, growth rate of the plate layer is fastest on the upper and lower sides of the through hole
300
(
FIG. 1
b
) due to easy access of electroplating solution. A consequence of this is that the upper and the tower region of the through hole
300
are likely to be filled first, thereby forming a hollow interior. This also happens to the opening side of the blind hole
310
. In brief, the process of forming a seed layer before electroplating produces an inter-layer conductive medium having a hollow center. To minimize such problem in the wire layout, width of an opening pad (&Dgr;r n
FIG. 3
) enclosing the hole is often increased and a connecting patch
410
is formed next to the hole to serve as landing pad for connecting with other layers. Ultimately, efficient utilization of surface area across a printed circuit board is not possible.
In addition, the absence of a solid interior in the inter-layer conductive medium fabricated by a conventional process also leads to other problems. For example, when a circuit pattern is fanned over the copper film
200
, a misalignment of the opening pad
140
(as shown in
FIG. 4
a
) may lead to an over-etching of the copper layer
200
(as shown in
FIG. 4
b
). The over-etched copper layer
200
may lead to poor electrical connection or electrical failure. To reduce such connectivity problems, the conventional remedy includes increasing the area of the opening pad
140
. However, increasing hole pad area reduces area, utilization of the printed circuit board.
In short, a conventional fabrication method produces a hollow conductive metallic ring that leads to a low utilization of printed circuit area and a low yield for the inter-layer conductive connection.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a solid inter-layer conductive rod capable of increasing area utilization of a printed circuit board and raising production yield of the inter-layer conductive connection.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.
One major aspect of this invention is the use of the second conductive layer as a negative electrode in the electroplating process. Without passing any electric current to the first conductive layer, conductive material starts to accumulate from the second conductive layer until the first and the second opening are completely filled. Since the upper portion of the opening is not blocked by conductive material early on in the process, a solid conductive rod is ultimately formed.
A second aspect of this invention is that the upper area of the solid conductive rod can be directly used as the conductive pad of a lower layer. There is no need to increase area of the opening pad or to form a connecting patch in neighboring area to serve as a conductive pad. Thus, area utilization of the printed circuit board is improved.
A third aspect of this invention is that conditions for forming a conductive layer over the solid conductive rod by photolithography and etching are less stringent because tolerance for hole pad misalignment is increased and the production of defective inter-layer electrical connection is less frequent. Ultimately, a higher product yield is obtained.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5567329 (1996-10-01), Rose et al.
Cheng Jao-Chin
Fan Chih-Peng
Hsieh Chang-Chin
Yeh Chih-Hao
J.C. Patent
Unimicron Taiwan Corp.
Wong Edna
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