Method of fabricating integrated devices

Fishing – trapping – and vermin destroying

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437 44, 437 52, 257316, 257326, H01L 218247, H01L 21266

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active

054647843

ABSTRACT:
A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.

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J. E. Moon et al., IEEE Electron Device Letters, vol. 11, No. 5, pp. 221-223, "A New LDD Structure: Total Overlap With Polysilicon Spacer (TOPS)," May 1990.
T. Huang et al., IEEE Electron Device Letters, vol. EDL-8, No. 4, pp. 151-153, "A New LDD Transistor with Inverse-T Gate Structure," Apr. 1987.
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