Method of fabricating integrated circuits with oxidized isolatio

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438414, 438444, 438356, 438357, 438359, H01L 2176

Patent

active

060936207

ABSTRACT:
A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

REFERENCES:
patent: Re28653 (1975-12-01), Murphy
patent: 2981877 (1961-04-01), Noyce
patent: 3025589 (1962-03-01), Hoerni
patent: 3064167 (1962-11-01), Hoerni
patent: 3117260 (1964-01-01), Noyce
patent: 3136897 (1964-06-01), Kaufman
patent: 3150299 (1964-09-01), Noyce
patent: 3156591 (1964-11-01), Hale et al.
patent: 3189798 (1965-06-01), Benjamin
patent: 3210620 (1965-10-01), Lin
patent: 3210677 (1965-10-01), Lin et al.
patent: 3241010 (1966-03-01), Eddelston
patent: 3260902 (1966-07-01), Porter
patent: 3290753 (1966-12-01), Chang
patent: 3296040 (1967-01-01), Wigton
patent: 3341755 (1967-09-01), Husher et al.
patent: 3370995 (1968-02-01), Lowery et al.
patent: 3386865 (1968-06-01), Doo
patent: 3391023 (1968-07-01), Fresura
patent: 3404450 (1968-10-01), Karcher
patent: 3404451 (1968-10-01), So
patent: 3442011 (1969-05-01), Strieter
patent: 3474308 (1969-10-01), Kronlage
patent: 3488564 (1970-01-01), Crafts
patent: 3489961 (1970-01-01), Frescura et al.
patent: 3500139 (1970-03-01), Frouin
patent: 3506502 (1970-04-01), Nakamura
patent: 3510735 (1970-05-01), Potter
patent: 3511702 (1970-05-01), Jackson, Jr. et al.
patent: 3513364 (1970-05-01), Heiman
patent: 3514846 (1970-06-01), Lynch
patent: 3534234 (1970-10-01), Clevenger
patent: 3550292 (1970-12-01), Irie et al.
patent: 3575740 (1971-04-01), Castrucci et al.
patent: 3575741 (1971-04-01), Murphy
patent: 3576683 (1971-04-01), Matsubara
patent: 3596149 (1971-07-01), Makimoto
patent: 3598664 (1971-08-01), Kilby
patent: 3602981 (1971-09-01), Kooi
patent: 3602982 (1971-09-01), Kooi
patent: 3615929 (1971-10-01), Portnoy
patent: 3640806 (1972-02-01), Watanabe et al.
patent: 3649386 (1972-03-01), Murphy
patent: 3736193 (1973-05-01), Tucker et al.
patent: 3858231 (1974-12-01), Magdo et al.
patent: 3861968 (1975-01-01), Magdo et al.
patent: 4118728 (1978-10-01), Berry
Agusta et al., "Component Interconnection for Integrated Circuits," IBM Technical Disclosure Bulletin, vol. 8, No. 12, May 1966, pp. 1843-1844.
Appels et al., "Local Oxidation of Silicon and Its Application in Semiconductor-Device Technology," Philips Research Reports, vol. 25, 1970, pp. 118-132.
Baker et al., "Oxide Isolation Brings High Density to Production Bipolar Memories," Electronics, Mar. 1973, pp. 65-70.
Bhola et al., "Epitaxial Deposition of Silicon by Thermal Decomposition of Silane," RCA Review, Dec. 1963, pp. 511-522.
Burger et al., Fundamentals of Silicon Integrated Device Technology, vol. 1, Oxidation, Diffusion and Epitaxy (Prentice Hall Inc.), 1967.
Doo et al., "Making Monolithic . . . Insulation and Junction Isolation Technology," IBM Technical Disclosure Bulletin, vol. 8, No. 4, Sep. 1965, pp. 659-660.
Jones et al., "A Composite Insulator-Junction Isolation," Electrochemical Technology, vol. 5, No. 5-6, May, Jun. 1967, pp. 308-310.
Kooi et al., LOCOS Devices, Philips Research Reports, vol. 26, Mar. 1971, pp. 166-180.
Kooi et al., "Locos Techniek voor Bipolaire Transistors, "Philips Technisch Tijdschrift, vol. 31, No. 11/12, 1970, p. 381.
Maheux, "Transistors for Monolithic Circuits," IBM Technical Disclosure Bulletin, vol. 11, No. 12, May 1969, pp. 1690-1691.
Murphy et al., "Collector Diffusion Isolated Integrated Circuits," Proceedings of the IEEE, vol. 57, No. 9, 1969, pp. 1523-1527.
"Process Cuts IC Cost," Electro Technology, Feb. 1970, p. 11.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating integrated circuits with oxidized isolatio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating integrated circuits with oxidized isolatio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating integrated circuits with oxidized isolatio will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1335961

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.