Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1999-04-12
2001-12-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S123000, C438S124000, C438S119000
Reexamination Certificate
active
06331452
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit (I.C.) die packaging. More particularly, this invention relates to an I.C. die package that allows direct interface between the I.C. die and its external environment, and methods of manufacturing the package.
BACKGROUND OF THE INVENTION
Packaging of electronic circuits is the science and the art of establishing interconnections and a suitable operating environment for the circuits to process or store information. The packaging must reconcile and satisfy application requirements with respect to cost, performance, and reliability, as well as constraints imposed by the laws of nature and the properties of materials and processes. Generally, environmental conditions such as temperature extremes, high relative humidity, mechanical shock and vibrations, electromagnetic fields, electrostatic discharges, and nuclear radiation may contribute to failures of electronic packages.
Currently, there are many different shapes and sizes of semiconductor packages available, including laminated ceramic, pressed ceramic, and molded plastic packages. In accordance with the laminated ceramic technology, a semiconductor die is attached to a ceramic package having leads extending from a lead frame. Bonding pads on the die are connected to the leads using bonding wires. A cap is then soldered to the ceramic package, thereby sealing the die and inner portions of the leads within the package.
In pressed ceramic technology, a semiconductor die is attached to a lower portion of a ceramic package having leads extending from a lead frame. After the wire bonding procedure, a top portion of the ceramic package is soldered to the lower portion of the ceramic package to seal the die and the inner portions of the leads within the package. Ceramic packaging is relatively expensive and the ceramic material causes a relatively large inductance, thus slowing down the signal propagation through the device.
With molded plastic technology, a semiconductor die is configured for housing within a plastic package from which a set of leads will extend.
FIGS. 1 through 5
and
6
A-
6
C illustrate the general process flow for a plastic molded I.C. package assembly.
FIG. 1
shows a conventional lead frame
10
having outwardly extending leads
12
. Lead frame
10
is the central supporting structure of the package to which every other element is attached. Etched or stamped from a thin sheet-metal strip into a filigree of narrow beams that radiate from a center platform, lead frame
10
carries the chip throughout the assembly process and becomes an integral part of the package after molding.
An I.C. die
14
is attached to lead frame
10
with a conductive adhesive
16
, as shown in FIG.
2
.
FIG. 3
shows I.C. die
14
electrically connected to the radiating beams (not shown) of lead frame
10
with fine-diameter bond wires
20
between bond pad
18
on I.C. die
14
and bond pad
19
on lead frame
10
, bond pad
19
being electrically coupled to one of the leads
12
. This assembly of I.C. die
14
, bond wires
20
, and lead frame
10
is placed in an injection molding device
22
that has a cavity
24
and an opening
26
for injecting a molding compound into cavity
24
, as shown in FIG.
4
. I.C. die
14
, bond wires
20
, and lead frame
10
are covered with the molding compound during the injection molding process, which is carried out at a high temperature. Conventional materials used for the molding compounds are novolac-based molding compounds.
Injection molding device
22
is pulled apart, leaving a plastic package
28
with leads
12
extending from plastic package
28
, as shown in FIG.
5
. Leads
12
are trimmed, formed, and tin-plated to complete the package.
FIG. 6A
shows leads
12
formed into butt joint leads
12
a
.
FIG. 6B
shows leads
12
formed into J-leads
12
b
.
FIG. 6C
shows leads
12
formed into gull wing leads
12
c.
The various packaging structures and methods described above may be sufficient for a traditional I.C. die. However, in the field of biometric identification, e.g., fingerprint identification, where the surface of the I.C. die must directly interface with its external environment, e.g., the finger, such structures and methodologies are incompatible because the I.C. die is encapsulated in various ways in the package. Efforts have been made to build an I.C. die package that leaves open the surface of the chip. One example is the package described in U.S. Pat. No. 5,862,248 (hereinafter, the '248 patent) issued on Jan. 19, 1999, to Salatino et al. and assigned to Harris Corporation, which is incorporated by reference herein in its entirety.
The '248 patent describes an integrated circuit device having an opening exposing the integrated circuit die to the sensed medium, such as a finger, and related methods. In particular, the '248 patent describes a package that includes an integrated circuit die
54
mounted on a lead frame
50
during injection molding to form the body of encapsulating material of the package, as shown in FIG.
7
. Electrical connections are made by bond wires
60
between bond pads
58
on I.D. die
54
and bond pads
59
on lead frame
50
, each of bond pads
59
is electrically coupled to corresponding outwardly extending leads
65
. The upper surface of the package includes an integrally molded opening
70
that directly permits contact to integrated circuit die
54
.
In the embodiment shown in
FIG. 7
, the upper mold portion
61
includes a body
62
and a notch
63
extending downwardly from body
62
. Upper mold portion
61
is brought into contact with lower mold portion
64
and clamped. Plastic encapsulating material is injected into cavity
68
, forming the plastic package. One important drawback for this method is that integrated circuit die
54
may be crushed by the extremely high-pressure associated with such process, even if high-temperature silicon rubber, which is highly compressible, is used as the mold material. Another drawback of the above method is the extreme difficulty in aligning notch
63
to integrated circuit die
54
.
A second embodiment of the '248 patent also employs injection molding to build an I.C. die package. As shown in
FIG. 8
, electrodes
85
, a body
82
of dissolvable material, and an adhesive layer
83
on the underside of electrodes
85
are aligned over and positioned onto the integrated circuit die
84
that, in turn, has been secured and connected to lead frame
80
. The above structure is positioned within a conventional integrated circuit package injection mold (not shown). After removal from the injection mold, the structure is positioned in a bath
86
containing a liquid solvent
87
, so that body
82
of dissolvable material is dissolved away, leaving an opening to the underlying portion of the integrated circuit die
84
. This method is undesirable because it requires additional processing steps and is thus more complicated and costly.
The molded plastic technology, in general, has several drawbacks. For example, the molded plastic technology incorporates various processes following the wire bonding procedure that may detrimentally affect the bonding integrity. These processes include sealing, which involves high-pressure injection-molding and cooling/heating steps, and the bending of the leads to achieve desired lead configurations, whereby bonding wire movement, breakage, and/or shorting can all result. Moreover, the encapsulation process is limited to the use of molding compounds with low thermal conductivity that can perform poorly.
Additionally, the use of lead frames during the manufacturing of semiconductor packages has many disadvantages. First, the dies from which conventional lead frames are stamped can be very expensive because of the number of intricate features of the circuit involved and the amount of material that must be handled. Moreover, the manufacturing tolerances required in stamping the larger sizes of necessary elements of the circuit cause the stamping of lead frames to be a low-yield process.
Bowers Charles
Lyon & Lyon LLP
Pert Evan
Verdicom, Inc.
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