Method of fabricating integrated circuit chip package

Details Method of fabricating integrated circuit chip package Method of fabricating integrated circuit chip package

1992-12-23

1994-11-29

Echols, P. W.

Metal working

Method of mechanical manufacture

Electrical device making

29593, H05K 334

Patent

active

053677650

ABSTRACT:
A method of fabricating an integrated circuit chip package is provided in which a multi-chip module is formed by mounting a plurality of IC chips on a single silicon circuit board by means of flip-chip interconnection. Compared with a conventional multi-chip module in which, in order to obtain a uniform gap between IC chips and a silicon circuit board, metal bumps provided on both the silicon circuit board and the IC chips are used, such gap is defined in the present method by thicknesses of organic insulating films formed on both the IC chips and the circuit board. That is, height of metal bumps is selected such that it is smaller than a sum of the thicknesses of the insulating films and that closed spaces due to melting of solder for metal bump connection is prevented from being formed between the organic insulating films.

REFERENCES:
patent: 4818728 (1989-04-01), Rai et al.
patent: 5075965 (1991-12-01), Carey et al.
1990 Symposium on VLSI Technology, Digest on Technical Papers, 4-7 Jun. 1990, pp. 95-96, Hayashi et al., "Fabrication of three-dimensional IC using Cumulatively Bonded IC (CUBIC) technology".
Patent Abstracts of Japan, vol. 14, No. 441, 20 Sep. 1990 (2-174153).
Patent Abstracts of Japan, vol. 12, No. 402, 25 Oct. 1988 (63-141356).
Patent Abstracts of Japan, vol. 14, No. 156, 26 Mar. 1990 (2-14536).

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