Method of fabricating IC chips with equation estimated peak cros

Details Method of fabricating IC chips with equation estimated peak cros Method of fabricating IC chips with equation estimated peak cros

1995-02-09

1997-01-21

Teska, Kevin J.

Boots, shoes, and leggings

H04B 332

Patent

active

055965067

ABSTRACT:
In one method according to the present invention, an integrated circuit chip is fabricated by the following steps:

REFERENCES:
patent: 5196733 (1993-03-01), Shin
patent: 5281867 (1994-01-01), Campbell, Jr. et al.
patent: 5341325 (1994-08-01), Nakano et al.
patent: 5481695 (1996-01-01), Purks
Accurate Measurement of High-Speed Package and Interconnect Parasitics IEEE, 1989.
A Facility For Near End Crosstalk Measurements On ISDN Subscriber Loops IEEEM 1989.
Modelling Of Crosstalk Among The Gaas-Based VLSI Interconnections.

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