Method of fabricating high yield wafer level packages...

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S106000, C438S121000

Reexamination Certificate

active

07067397

ABSTRACT:
Monolithic microwave integrated circuit (MMIC) components and micro electromechanical systems (MEMS) components are integrated onto a single substrate at a wafer scale, by first performing MMIC and MEMS fabrication on a front face of a thick substrate wafer, bonding the substrate wafer to a cover wafer, thinning the back face of the substrate wafer and, finally, completing MMIC and MEMS fabrication on the back face of the thinned substrate wafer. The fabrication process is facilitated by use of a guard ring between the wafers to provide additional mechanical support to the substrate wafer and to protect the devices while the MMIC/MEMS fabrication is completed, and by a low temperature bonding process to join the substrate wafer and the cover wafer at multiple device cavity seal rings.

REFERENCES:
patent: 3615855 (1971-10-01), Smith
patent: 5448014 (1995-09-01), Kong et al.
patent: 6297072 (2001-10-01), Tilmans et al.
patent: 6323550 (2001-11-01), Martin et al.
patent: 6326697 (2001-12-01), Farnworth
patent: 6400021 (2002-06-01), Cho
patent: 6420244 (2002-07-01), Lee
patent: 6441481 (2002-08-01), Karpman
patent: 6455353 (2002-09-01), Lin
patent: 6465280 (2002-10-01), Martin et al.
patent: 6465281 (2002-10-01), Xu et al.
patent: 6534340 (2003-03-01), Karpman et al.
patent: 6534341 (2003-03-01), Farnworth
patent: 6555417 (2003-04-01), Spooner et al.
patent: 6597066 (2003-07-01), Farnworth et al.
patent: 6621158 (2003-09-01), Martin et al.
patent: 6635509 (2003-10-01), Ouellet
patent: 6710461 (2004-03-01), Chou et al.
patent: 6777263 (2004-08-01), Gan et al.
patent: 2003/0173017 (2003-09-01), Hecht et al.
Sovero E A, Mihailovich R, Deakin D S, Higgins J A, Yao J J, DeNatale J F and Hong J H Monolithic GaAs PHEMT MMIC's integrated with high performance MEMS microrelays Proc. IMOC '99, Rio de Janeiro, Brazil (Aug. 9-12, 1999).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating high yield wafer level packages... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating high yield wafer level packages..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating high yield wafer level packages... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3630590

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.