Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
1999-10-28
2001-08-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S270000, C438S443000
Reexamination Certificate
active
06277675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for an integrated circuit. More particularly, the present invention relates to a method for fabricating a high voltage (HV) MOS device.
2. Description of Related Art
A technique for fabricating HV MOS devices is described in the article entitled “High Voltage Thin layer Devices (RESURF Devices),” IEDM Proceedings, 1979, pp 238-241. This technique uses a shallow lightly doped region between the drain and channel regions of the device. This shallow lightly doped region is referred to as a drift region because of the low amount of current carriers that are available due to the low level of impurity doping, while the device is known as a Reduced Surface Field, RESURF, device.
RESURF techniques are utilized in manufacturing high voltage N-channel Lateral Double Diffused MOS, LDMOS, devices and high voltage, P-channel LDMOS, devices. However, problems exist in the manufacture of such RESURF LDMOS devices.
FIG. 1
is a schematic, cross-sectional diagram illustrating a conventional LDMOS structure.
Referring to
FIG. 1
, a p-type substrate
100
is provided with a field oxide layer
102
formed on the surface thereof, wherein the field oxide layer
102
serves to increase the channel length between a N-type source region
104
and a N-type drain region
106
. A N-type lightly doped region
108
which serves as a drift region for carriers after voltage application to the device is formed below the field oxide layer
102
in the substrate
100
. A P-type lightly doped region
112
is formed below a gate electrode
110
and surrounding the N-type source region
104
to increase the internal electric field of the device. As a result, the trans conductance of the device is improved under this circumstance. However, a denser distribution of electric line with larger curvature is produced below a channel region
114
and around the edge of the drift region
108
to result in a potential crowding when the device is operated at a high voltage. The depletion region formed by the drift region
108
is not sufficient to lessen the distribution of the electric line produced by high voltage; thus the increased electric field causes an electrical breakdown adjacent to the channel region of the device instead of in a bulk region. The bulk region is indicated as a part of the substrate
100
at the drain end of the device.
Conventionally, the problem of electrical breakdown is solved by reducing the doping concentration of the drift region
108
as a way to increase the size of the depletion region, while such size increase of the depletion region results in an increase in breakdown voltage. However, the current driving performance of the device is decreased when the concentration in the drift region
108
is decreased, while the electrical breakdown rarely occurs in the bulk region. Furthermore, since the channel length
114
cannot be precisely controlled using the gate electrode
110
that serves as a mask, it is difficult to increase the electric field strength, which in turn affects the conductance of the device.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a high voltage MOS device, which method includes providing a substrate with a first P-type well region and a N-type type well region formed thereon. A field oxide is then formed on the N-well region and patterned until field oxide projections project from the field oxide layer. With the field oxide projections serving as masks, second P-type well regions are formed in both P-type and N-type lightly doped well regions. A patterned gate oxide layer and a gate polysilicon layer are formed in sequence to cover a part of the field oxide layer and the field oxide projection, wherein the gate oxide layer and the gate polysilicon layer form a to gate electrode. With the gate electrode and the field oxide layer serving as masks, a source/drain region is consequently formed in the first P-type well region and the N-type well region, respectively.
As embodied and broadly described herein, the invention provides a HV MOS device comprising a first P-well region, a N-well region, and a second P-well region, wherein the second P-well region has a higher doping concentration than the first P-well region and the N-well region. Therefore, the second P-well region can increase the conductance in the device due to its high doping concentration. In addition, the N-well region has a higher doping concentration in comparison with the conventional drift region, so the electrical breakdown occurs more readily in the bulk region rather than in the channel region. This implies that a higher voltage can be applied to the device without causing the electrical breakdown that would damage the device. Furthermore, the threshold voltage applied to the device can be adjusted through the first P-well due to a difference in doping concentrations of the first P-well and the second P-well.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5770880 (1998-06-01), Woodbury et al.
patent: 5970343 (1999-10-01), Kocon
patent: 6037229 (2000-03-01), Lee
Chaudhari Chandra
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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