Method of fabricating high-voltage CMOS device

Details Method of fabricating high-voltage CMOS device Method of fabricating high-voltage CMOS device

2007-08-07

2007-08-07

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making regenerative-type switching device

Having field effect structure

C438S197000, C438S303000

Reexamination Certificate

active

11022847

ABSTRACT:
The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.

REFERENCES:
patent: 6211552 (2001-04-01), Efland et al.
patent: 6424005 (2002-07-01), Tsai et al.

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