Method of fabricating high density high breakdown voltage CMOS d

Details Method of fabricating high density high breakdown voltage CMOS d Method of fabricating high density high breakdown voltage CMOS d

1981-10-21

1984-01-24

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29579, 29580, 148187, H01L 21265

Patent

active

044267665

ABSTRACT:
A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.

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patent: 4315781 (1982-02-01), Henderson
"RCA COS/MOS Integrated Circuits Manual", RCA Corp., 1971, pp. 1, 24 and 25.

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