Method of fabricating high breakdown voltage FETs

Details Method of fabricating high breakdown voltage FETs Method of fabricating high breakdown voltage FETs

1994-07-05

1996-05-07

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437912, 437176, 437184, H01L 21338

Patent

active

055146066

ABSTRACT:
A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.

REFERENCES:
patent: 4540446 (1985-09-01), Nonaka et al.
patent: 5001076 (1991-03-01), Mikkelson
patent: 5041393 (1991-08-01), Ahrens et al.
patent: 5196359 (1993-03-01), Shih et al.
Chang-Lee Chen et al., "High-Breakdown-Voltage MESFET with a Low-Temperature-Grown GaAs Passivation Layer and Overlapping Gate Structure", IEEE Electron Device Letters, vol. 13, No. 6, Jun. 1992, pp. 335-337.
F. W. Smith et al., "A 1.57 W/mm GaAs-Based MISFET for High-Power and Microwave-Switching Applications", 1991 IEEE MTT-S Digest, pp. 643-646.

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