Method of fabricating gate stack having a reduced height

Details Method of fabricating gate stack having a reduced height Method of fabricating gate stack having a reduced height

1994-01-03

1995-08-01

Thomas, Tom

Fishing, trapping, and vermin destroying

437233, 437246, 437913, 148DIG105, H01L 218232

Patent

active

054380065

ABSTRACT:
An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

REFERENCES:
patent: 4885259 (1989-12-01), Osinski et al.
patent: 4886764 (1989-12-01), Miller et al.
patent: 4971655 (1990-11-01), Stefano et al.
patent: 5034348 (1991-07-01), Hartswick et al.
patent: 5094712 (1992-03-01), Becker et al.
patent: 5302538 (1994-04-01), Ishikawa et al.
patent: 5346586 (1994-09-01), Keller

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