Method of fabricating fin field-effect transistors

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S294000, C438S404000, C438S443000, C257SE21545, C257SE21546

Reexamination Certificate

active

07348254

ABSTRACT:
A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming a first insulating layer and a second insulating layer on a region of a substrate excluding an inactive region thereof; forming a trench of the inactive region of the substrate by using the first and second insulating layers as a mask; forming an element isolation layer in the trench; and removing the first insulating layer and the second insulating layer and, at the same time, removing a predetermined thickness of the element isolation layer.

REFERENCES:
patent: 5949126 (1999-09-01), Dawson et al.
patent: 7176530 (2007-02-01), Bulucea et al.
patent: 2005/0167778 (2005-08-01), Kim et al.

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