Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2000-07-26
2001-08-21
Ramsey, Kenneth J. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
C445S050000
Reexamination Certificate
active
06276982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of fabricating field emission arrays. Particularly, the present invention relates to field emission array fabrication methods wherein the emitter tips and their corresponding resistors are fabricated through a single mask. More particularly, the present invention relates to field emission array fabrication methods that employ only one mask to define the emitter tips and their corresponding resistors and that do not require a mask to define the column lines thereof.
2. Background of the Related Art
Typically, field emission displays (“FEDs”) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extends over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro-luminescent panel, the pixel is illuminated. The degree to which the pixel is illuminated depends upon the number of electrons that impact the pixel.
Numerous techniques have been employed to fabricate field emission arrays and the resistors thereof. An exemplary field emission array fabrication technique includes fabricating the column lines and emitter tips prior to fabricating a dielectric layer and the overlying grid structure, such as by the methods of U.S. Pat. No. 5,302,238, issued to Fred L. Roe et al. on Apr. 12, 1994, and U.S. Pat. No. 5,372,973, issued to Trung T. Doan et al. on Dec. 13, 1994. Alternatively, a field emission array may be fabricated by forming the dielectric layer and the overlying grid structure, then disposing material over the grid structure and into openings therethrough to form the emitter tips, such as by the technique disclosed by U.S. Pat. No. 5,669,801, issued to Edward C. Lee on Sep. 23, 1997. Such conventional field emission array fabrication methods typically require the use of masks to independently define the various features, such as the column lines, resistors, and emitter tips, thereof.
Another exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,374,868 (hereinafter “the '868 Patent”), issued to Kevin Tjaden et al. on Dec. 20, 1994. The fabrication method of the '868 Patent includes defining trenches in a substrate. The trenches correspond substantially to columns of pixels of the field emission array. A layer of insulative material is disposed over the substrate, including in the trenches thereof. A layer of conductive material and a layer of cathode material (e.g., polysilicon) are sequentially disposed over the layer of insulative material. A mask may then be disposed over the layer of cathode material and the emitter tips and their corresponding column lines defined through the cathode material and “highly conductive” material layers, respectively. The method of the '868 Patent is, however, somewhat undesirable in that the mask thereof is not also employed to fabricate resistors, which limit high current and prevent device failure. Moreover, in the embodiment of the method of the '868 Patent that employs a single mask to fabricate both the emitter tips and their corresponding column lines, neither the “highly conductive” material nor the cathode material is planarized. Thus, the layer of cathode material may have an uneven surface and the heights of the emitter tips defined therein may vary substantially. In embodiments of the method of the '868 Patent where the layer of “highly conductive” material is planarized, only the emitter tips are defined through the mask.
Accordingly, there is a need for a field emission array fabrication process that employs a minimal number of mask steps to define emitter tips of substantially uniform height, their corresponding resistors, and their corresponding column lines.
BRIEF SUMMARY OF THE INVENTION
The present invention includes a method of fabricating the pixels of a field emission array and, in particular, defining emitter tips and their corresponding resistors by employing a single mask. The field emission array fabrication method of the present invention may also include electrically isolating adjacent column lines from one another with requiring the use of an additional mask. Field emission arrays fabricated in accordance with the inventive method are also within the scope of the present invention.
The method of the present invention includes defining a plurality of substantially mutually parallel conductive lines on a substrate. In order to define the conductive lines, a layer of conductive material may be deposited onto the substrate. The conductive lines may be defined from the conductive layer by known processes. Alternatively, conductive material may be selectively deposited onto the substrate, as known in the art, to define the conductive lines.
One or more layers of semiconductive material or conductive material, from which the emitter tips and their corresponding resistors of the field emission array will be defined, may be disposed over each of the conductive lines and over the regions of the substrate that are exposed between adjacent conductive lines. The layer or layers of semiconductive material or conductive material are also referred to herein as the emitter tip-resistor layer or as the emitter tip layer and resistor layer, respectively. The emitter tip and resistor layer or layers may be disposed over the conductive lines and the substrate by known processes and in a thickness that corresponds to a desired height of the emitter tips and their corresponding resistors. As each of the conductive lines protrudes somewhat from the surface of the substrate, a cross section of the emitter tip and resistor layer or layers has a peak and valley appearance. The peaks of the emitter tip and resistor layer or layers are disposed substantially above the conductive lines, while the valleys of the emitter tip and resistor layer or layers are disposed substantially between adjacent column lines. Due to this peak and valley appearance, if the emitter tip and resistor layer or layers are planarized, the height of the emitter tips and the resistors are defined somewhat by the relative heights of the conductive lines and the thickness of material remaining above the conductive lines following planarization.
A layer of mask material may be disposed over the emitter tip and resistor layer or layers. Such a mask material may be removed from substantially above the conductive lines (i.e., from above the “peaks”) by known processes to define a so-called “hard mask” from the remaining mask material (i.e., the regions located in the “valleys”). Upon exposure of regions of the emitter tip and resistor layer or layers, regions of the emitter tip and resistor layer or layers disposed above the substantially longitudinal center portion of each of the conductive lines may be substantial
Micro)n Technology, Inc.
Ramsey Kenneth J.
TraskBritt
LandOfFree
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