Method of fabricating electronic devices integrated in...

Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S471000, C257S913000

Reexamination Certificate

active

06709955

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of fabricating electronic devices, integrated in semiconductor substrates provided with gettering sites, and a device fabricated by this method.
Specifically, the invention relates to a method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one active area of the device, the method comprising at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in said semiconductor by evaporation of said noble gas.
The invention further relates to an electronic device integrated in a semiconductor substrate having at least one non-active area contiguous with at least one active area of said device.
The invention relates, particularly but not exclusively, to a method as above, which comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment that leads to the formation of getter bubbles in said semiconductor by evaporation of said noble gas. The ensuing description is referred to this field of application for convenience of explanation only.
BACKGROUND OF THE INVENTION
A requisite of this specific technical field is that metal contaminants, as are to be found normally in semiconductor substrates and may seriously affect the performance of integrated circuits in the substrates, be trapped out.
The presence of metal impurities in the lattice structure of silicon is, in fact, a constant source of problems and malfunction with semiconductor electronic devices. Thus it is that intensive research work is being carried out to rid the silicon of such metal impurities.
To address the problem, gettering techniques have been adopted, whereby semiconductor monolithically integrated electronic devices are provided with getters effective to trap out metal contaminants present in the semiconductor.
These getters are usually formed at the end of the integrated circuit fabricating process. For the purpose, the front side of the semiconductor wafer, where the circuits have been formed, is covered with a protective layer, and the back side of the wafer is cleaned and applied a POC13 deposition or phosphorus (P) ion implantation directed to create certain extensively damaged or defective areas in the semiconductor substrate.
These areas act as getters effective to attract and segregate metal atomic impurities, as explained hereinafter.
However, this prior gettering technique poses some problems due to that it is applied practically at the end of the fabrication process and may affect the performance of the circuits that have been formed in the semiconductor wafer. Also, because of the low solid-state solubility of phosphorus in silicon, the gettering efficiency of defects so created is not particularly high.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a method of fabricating devices with getters, which method has suitable features to enhance the trapping of metal atomic impurities without altering the device current flows, thus overcoming the drawbacks with which prior devices are beset.
The method enhances trapping of the impurities without altering the device current flows by having gettering sites produced and confined within non-active areas of electronic devices formed on a semiconductor.
z
The features and advantages of the device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


REFERENCES:
patent: 4371403 (1983-02-01), Ikubo et al.
patent: 5244819 (1993-09-01), Yue
patent: 5714395 (1998-02-01), Bruel
patent: 5840590 (1998-11-01), Myers, Jr. et al.
patent: 6103582 (2000-08-01), Lee et al.
patent: 6162705 (2000-12-01), Henley et al.
patent: 6168981 (2001-01-01), Battaglia et al.
patent: 6225192 (2001-05-01), Aspar et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 05235005 (1993-09-01), None
patent: 10032209 (1998-02-01), None
patent: 11074275 (1999-03-01), None
Raineri et al., “Gettering of Metals by Voids in Silicon,”Journal of Applied Physics, 78(6):3727-3735, Sep. 15, 1995.
Petersen et al., “Gettering of Transition Metals by Cavities in Silicon Formed by Helium Ion Implantation,”Nuclear Instruments and Methods in Physics Research, Section B, 127-128:302-306, May 1, 1997.
Zhangn et al., “Gettering of Cu by Microcavities in Bonded/Ion-Cut Silicon-on-Insulator and Separation by Implantation of Oxygen,”Journal of Applied Physics, 86(8):4214-4219, Oct. 15, 1999.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating electronic devices integrated in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating electronic devices integrated in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating electronic devices integrated in... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3221088

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.