Method of fabricating density intensive non-self-aligned stacked

Details Method of fabricating density intensive non-self-aligned stacked Method of fabricating density intensive non-self-aligned stacked

1984-04-27

1985-12-03

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576J, 148DIG164, 357 237, 357 42, H01L 2188, H01L 2120, H01L 21283

Patent

active

045558434

ABSTRACT:
A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capicitances.

REFERENCES:
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4476475 (1984-10-01), Naem et al.
Robinson, A. L. et al., "A Fully-Self-Aligned Joint-Gate CMOS Technology" in IEEE International Electron Devices Meeting, Technical Digest, Dec. 1983, pp. 530-533.

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