Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Treating electrolytic or nonelectrolytic coating after it is...
Reexamination Certificate
2002-06-19
2004-09-14
Koehler, Robert R. (Department: 1775)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Treating electrolytic or nonelectrolytic coating after it is...
C205S223000, C205S261000, C205S291000, C205S640000, C205S674000, C205S917000, C438S689000
Reexamination Certificate
active
06790336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of interlayer connections in semiconductor devices using a copper damascene structure.
2. Prior Art
In current integrated circuits, several layers of interconnect structures fabricated above a substrate containing active devices are often used. Each interconnect layer is fabricated in, or on, an interlayer dielectric (ILD). Vias are formed in each ILD to make contact with conductors in underlying layers. It is generally accepted that the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between the conductors.
Copper damascene structures are often used in conjunction with the ILDs to provide the interconnect structure. Typically, the copper is planarized using chemical-mechanical polishing (CMP) because of the difficulties of chemically etching copper.
A problem arises where low k dielectrics are used in conjunction with a copper damascene structure. The low k dielectrics are inherently mechanically weak, and consequently, not particularly suitable for the stresses associated with the CMP.
Articles discussing low k dielectrics are: “From tribological coatings to low-k dielectrics for ULSI interconnects,” by A. Grill, Thin Solid Films 398-399 (2001) pages 527-532; “Integration Feasibility of Porous SiLK Semiconductor Dielectric,” by J. J. Waeterloos, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 253-254; and “Low-k Dielectrics Characterization for Damascene Integration,” by Simon Lin, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 146-148.
REFERENCES:
patent: 5096550 (1992-03-01), Mayer et al.
patent: 6017437 (2000-01-01), Ting et al.
patent: 6143155 (2000-11-01), Adams et al.
patent: 6328872 (2001-12-01), Talieh et al.
Grill, A., “From tribological coatings to low-k dielectrics for ULSI interconnects,” Thin Solid Films 398-399 (2001), pp. 527-532. (no month given).
Lin, Simon, et al., “Low-k Dielectrics Characterization for Damascene Integration,” Conference Proceedings, IITC, Jun. 2001, pp. 146-148.
Waeterloos, J.J., et al.,“Integration feasibility of Porous SiLK Semiconductor Dielectric,” Conference Proceedings, IITC, Jun. 2001, pp. 253-254.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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