Method of fabricating complementary poly emitter transistors

Details Method of fabricating complementary poly emitter transistors Method of fabricating complementary poly emitter transistors

1994-11-14

1996-03-05

Fourson, George

Fishing, trapping, and vermin destroying

437 46, 437152, 437160, 437162, 437186, 437193, 148DIG10, 148DIG11, 148DIG18, 148DIG122, 148DIG123, 148DIG124, H01L 21265

Patent

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054967449

ABSTRACT:
In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors. According to the manufacturing method, the emitter regions have a uniform impurity concentration in an appropriate shape, thus reducing the variation and degradation of the characteristics of the device due to downsizing.

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patent: 5244835 (1993-09-01), Hachiya
patent: 5296388 (1994-03-01), Kameyama et al.

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