Method of fabricating CMOS-compatible non-volatile memory...

Details Method of fabricating CMOS-compatible non-volatile memory... Method of fabricating CMOS-compatible non-volatile memory...

2010-01-07

2010-11-23

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C438S524000, C438S160000

Reexamination Certificate

active

07839693

ABSTRACT:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

REFERENCES:
patent: 6413818 (2002-07-01), Huang et al.
patent: 7067875 (2006-06-01), Shukuri
patent: 7154779 (2006-12-01), Mokhlesi et al.
patent: 7294888 (2007-11-01), Paak et al.
patent: 2002/0196665 (2002-12-01), Kim
patent: 2004/0079988 (2004-04-01), Harari
patent: 2004/0120175 (2004-06-01), Schrom et al.
U.S. Appl. No. 11/974,361, filed Oct. 12, 2007, Paak et al.

Affiliated with

Also associated with

Rating

Method of fabricating CMOS-compatible non-volatile memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating CMOS-compatible non-volatile memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating CMOS-compatible non-volatile memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4166084